nusgart / uhdl_mister

A port of the UHDL CADR project to the MiSTer. Based off of https://tumbleweed.nu/r/uhdl and https://github.com/lisper/cpus-caddr.
GNU General Public License v2.0
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Template core for MiSTer

General description

This core contains the latest version of framework and will be updated when framework is updated. There will be no releases. This core is only for developers. Besides the framework, core demonstrates the basic usage. New or ported cores should use it as a template.

It's highly recommended to follow the notes to keep it standardized for easier maintenance and collaboration with other developers.

Source structure

Legend:

Standard MiSTer core should have following folders:

Other standard files:

PLL:

Framework implies use of at least one PLL in the core. Framework doesn't comtain this PLL but requires it to be placed in rtl folder, so pll folder and pll.v, pll.qip files must be present, however PLL settings are up to the core.

Verilog Macros

The following macros can be defined and will affect the framework features:

Macro Effect
ARCADE_SYS Disables the UART and OSD status
DEBUG_NOHDMI Disable HDMI-related modules. Speeds up compilation but only analogue/direct video is available
DUAL_SDRAM Changes configuration of FPGA pins to work with dual SDRAM I/O boards
USE_DDRAM Enables DDRAM ports of emu instance
USE_SDRAM Enables SDRAM ports of emu instance
USE_FB Allows to use framebuffer from the core

Quartus version

Cores must be developed in Quartus v17.0.x. It's recommended to have updates, so it will be v17.0.2. Newer versions won't give any benefits to FPGA used in MiSTer, however they will introduce incompatibilities in project settings and it will make harder to maintain the core and collaborate with others. So please stick to good old 17.0.x version. You may use either Lite or Standard license.