openXC7 nextpnr-xilinx issues

openXC7 / nextpnr-xilinx

Experimental flows using nextpnr for Xilinx devices

ISC License

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issues

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openXC7 - no Bels remaining of type 'BUFMR'

#55 kerimbavcic opened 1 week ago
1
ERROR: slave_oserdese has disconnected OQ/OFB output ports

#54 chili-chips-ba closed 2 weeks ago
1
fix oserdes pack bug

#53 AdamLee7 closed 2 weeks ago
1
ERROR: slave_oserdese has disconnected OQ/OFB output ports

#52 chili-chips-ba closed 2 weeks ago
1
json2dcp: replace deprecated RapidWright API; fix cell placement and routing

#51 hansemro opened 4 weeks ago
5
routing hangs for small 8k design without BRAMs

#50 mirekez opened 1 month ago
1
[primitives-fixes] xilinx: handle RAM128X1S's scalar address port; fix RAM256X1S INIT assignment

#49 hansemro closed 1 month ago
1
Changed boost library deprecated function in bbasm

#48 regymm closed 1 month ago
2
boost::filesystem::basename no longer exists

#47 yufrice closed 1 month ago
1
Signal name a[0:0]

#46 regymm opened 1 month ago
0
fix iddr and oddr pack port bug

#45 AdamLee7 closed 1 month ago
1
Faild to parse newly add data to architecture (chip_info) .bin file

#44 weikongwei closed 2 months ago
2
PLLE2_ADV: Support more compensation types, especially ZHOLD

#43 hansfbaier closed 2 months ago
0
warning: format '%d' expects on Arm64 M1Mac

#42 hsk closed 3 months ago
4
nextpnr cant route design - ERROR: Invalid global constant node 'INT_L_X0Y60/GND_WIRE'

#41 mirekez opened 3 months ago
2
nextpnr cant route design, Vivado works - ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.

#40 mirekez opened 3 months ago
1
nextpnr failed to route 6 RAMB36E1 design, gives ERROR: Failed to route arc 0 of net 'modules_2.mem_ext.Memory.0.8.genblk1.genblk1.CAS_B', from SITEWIRE/RAMB36_X3Y21/CASCADEOUTB to SITEWIRE/RAMB36_X2Y28/CASCADEINB

#39 mirekez opened 3 months ago
1
If N polarity pin is used as single clock BUFG, nextpnr gives error ERROR: Invalid global constant node 'INT_L_X0Y109/VCC_WIRE'

#38 mirekez opened 3 months ago
0
Unreadable error: ERROR: Port PCOUT40 has no connections - because of DSP in one design

#37 mirekez closed 3 months ago
0
nextpnr-xilinx crash when MONITOR_BOT_XXX pin is used as input or output data PAD

#36 mirekez closed 3 months ago
1
ERROR: Failed to route arc 0 of net '$abc$20823$aiger20822$2149', from SITEWIRE/DSP48_X0Y49/PCOUT23 to SITEWIRE/DSP48_X0Y51/PCIN23

#35 mirekez opened 3 months ago
1
fix Ibuf_ibufdisable

#34 lehaifeng000 closed 2 months ago
0
LUTRAM write occurs on rising edge regardless of IS_WCLK_INVERTED property

#33 hansemro opened 5 months ago
14
xilinx/pack_dram: log error on unsupported LUTRAM

#32 hansemro closed 5 months ago
2
gui/quadtree.h: drop const on max_elems_

#31 hansemro closed 5 months ago
2
xilinx/pack_dram: log error when packing RAM256X1D on XC7

#30 hansemro closed 5 months ago
1
Fix RAM32M/RAM64M initialization with INIT_{A,B,C,D} parameters

#29 hansemro closed 5 months ago
2
RAM32M/RAM64M not initialized with INIT_A/INIT_B/INIT_C/INIT_D parameters

#28 hansemro closed 5 months ago
14
add LUT6_2 support

#27 lehaifeng000 closed 5 months ago
4
xilinx/arch_place: validate BSCAN placement based on JTAG_CHAIN parameter

#26 hansemro closed 5 months ago
3
BSCANE2 placement not determined by JTAG_CHAIN parameter

#25 hansemro closed 5 months ago
4
fix 256 bit attr error

#24 lehaifeng000 closed 5 months ago
23
Properly handle "drive" attribute as string or numeric

#23 cestrauss closed 5 months ago
1
nice to meet you

#22 lehaifeng000 closed 5 months ago
7
Placer places posedge and negedge flip flops into the same slice

#21 jschj closed 10 months ago
14
Limited support for Distributed Memory / LUTRAM

#20 hansemro opened 11 months ago
36
Fix crashes

#19 engstad closed 1 year ago
2
Fix crashes

#18 engstad closed 1 year ago
0
Crash during DSP check_illegal_fanout

#17 gh-sh4 closed 1 year ago
12
Add validation/support for get_ports defined with brackets in XDC

#16 gh-sh4 closed 11 months ago
1
XDC Parsing fails without human-readable error

#15 gh-sh4 closed 11 months ago
6
oen signal of Tristate outputs is inverted by default in router1

#14 hansfbaier opened 1 year ago
0
Prioritize support of BSCANE2 and STARTUPE2 primitives

#13 chili-chips-ba closed 10 months ago
1
STA is very rudimentary, down to not even honoring timing constraints, yet alone accounting for clock tree skew

#12 chili-chips-ba opened 1 year ago
0
Error messaging does not provide enough info for the self-guided debug

#11 chili-chips-ba closed 1 month ago
3
Main analytical placer locks up for designs with high Distributed RAM usage.

#10 chili-chips-ba opened 1 year ago
0
Error Message by Constraining Positiv OBUFDS Output to negativ Pin Pair

#9 FeldmeierMichael opened 1 year ago
0
Add rules check for conflincting outputs

#8 Tobias-DG3YEV opened 1 year ago
0
Add support for pin drive strength

#7 Tobias-DG3YEV closed 5 months ago
1
The link to the manual RapidWright installation does no longer exist

#6 Tobias-DG3YEV closed 1 month ago
0