openFPGAloader support - Githubissues

rwhitby commented 2 years ago

I have purchased 5 of the QMTech boards for work purposes (arriving later this week), so should be able to use one to experiment with the open source flow. I also have (limited) access to the Genesys2 board.

I would like to add support to openFPGAloader, but the QMTech board does not have a standard USB-JTAG solution on-board.

What JTAG solution is everyone using for the QMTech board? It looked to me that the Digilent-HS2 might be a reasonable solution, or a Tigard perhaps.

If there is a popular choice, I would purchase and use that adapter and then contribute openFPGAloader for that board/adapter combination.

hansfbaier commented 2 years ago

Hi, openFPGAloader already supports the FPGA, you can use any adapter openFPGAloader supports. I personally use a cheap noname $10 FT232H board. I certainly can recommend the tigard, which is a similar board (using the FT2232).

rwhitby commented 2 years ago

Yes, openFPGAloader supports the FPGA and numerous adapters that will work with the FPGA.

I was hoping to contribute board support, so that the QMTech board (with it's built-in SPI flash in particular) is supported as a board, eventually allowing a command line such as

openFPGAloader -b qmtechK7325T -f combined_bitstream_and_firmware.mcs

to flash the SPI with a combined bitstream and firmware for a soft RISC-V processor with XIP QSPI support.

If there was a common JTAG adapter choice which the majority of users of this board are using already, then supporting this combination as a --board option could be a convenience, rather than always needing to provide the --fpga-part and --cable options.

rwhitby commented 2 years ago

For example, in board.hpp, adding:

JTAG_BOARD("qmtechK7325T",    "xc7k325t", "<what-would-be-best-here?>",     0, 0, CABLE_DEFAULT),

Proposed options being:

JTAG_BOARD("qmtechK7325T",    "xc7k325t", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("qmtechK7325T",    "xc7k325t", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("qmtechK7325T",    "xc7k325t", "ft232", 0, 0, CABLE_DEFAULT),

hansfbaier commented 2 years ago

Good question, hard to tell. The cheapest are the generic ft232h boards but the ft2232h are very common too. I would probably go for the ft2232h, maybe.

somhi commented 2 years ago

I'm using an FT2232H recommended by @benitoss. It is the first one pictured here https://github.com/benitoss/ColorLight_FPGA_boards It can work as a Xilinx cable or as an USB blaster also for Altera boards, just changing it's firmware.

benitoss commented 2 years ago

You can use OpenOCD to program the kintex7 QMTECH fpga, but writting the SPI Flash will not work.

rwhitby commented 2 years ago

[Edit: I didn't realise you said OpenOCD rather than openFPGAloader. I'm intending to use openFPGAloader.]

Not even with spiOverJtag support?

I'm currently doing that with an Arty A7-100T and assumed the same mechanism could be made possible on the K7-325T ...

rwhitby commented 2 years ago

OK, I've received my boards, and have built and flashed blinky.bit successfully with openFPGAloader.

Time to start researching how to create a spiOverJtag_xc7k325tffg676.bit file.

rwhitby@inxs iqmc510x_fw % openFPGALoader -c tigard --dump-flash foo.bin -v --fpga-part xc7k325t --file-size 0x1000
Jtag frequency : requested 6.00MHz   -> real 6.00MHz
found 1 devices
index 0:
    idcode 0x3651093
    manufacturer xilinx
    family kintex7
    model  xc7k325t
    irlength 6
File type : bin
use: /usr/local/Cellar/openfpgaloader/0.7.0/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
Error: fail to open /usr/local/Cellar/openfpgaloader/0.7.0/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
libc++abi: terminating with uncaught exception of type std::runtime_error: Error: fail to open /usr/local/Cellar/openfpgaloader/0.7.0/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
zsh: abort      openFPGALoader -c tigard --dump-flash foo.bin -v --fpga-part xc7k325t  0x1000
rwhitby@inxs iqmc510x_fw % ls /usr/local/Cellar/openfpgaloader/0.7.0/share/openFPGALoader
spiOverJtag_10cl025256.rbf      spiOverJtag_xc6slx45csg324.bit      spiOverJtag_xc7a35tftg256.bit
spiOverJtag_5ce223.rbf          spiOverJtag_xc7a100tcsg324.bit      spiOverJtag_xc7a50tcpg236.bit
spiOverJtag_5ce423.rbf.gz       spiOverJtag_xc7a100tfgg484.bit      spiOverJtag_xc7a75tfgg484.bit
spiOverJtag_ep4ce1523.rbf.gz        spiOverJtag_xc7a200tsbg484.bit      spiOverJtag_xc7s25csga324.bit.gz
spiOverJtag_ep4ce2217.rbf       spiOverJtag_xc7a35tcpg236.bit       spiOverJtag_xc7s50csga324.bit.gz
spiOverJtag_xc6slx100fgg484.bit     spiOverJtag_xc7a35tcsg324.bit       test_sfl.svf
rwhitby@inxs iqmc510x_fw %

I've found xilinx_spiOverJtag.v and xilinx_spiOverJtag.tcl, and I'm wondering if the correct path is to use a Vivado license for the K7-325T to add that device to the tcl file and build a bitstream ...

jrrk2 commented 2 years ago

Genesys2 does not require any adaptor, the Digilent USB2JTAG sub-module is on board already. RAM programming may readily be done with:

openFPGALoader --cable digilent --bitstream blinky.bit --ftdi-channel 1

Programming flash is done by reprogramming the FPGA as a flash programmer. I am not aware of whether there is an existing open source technique we can use for this

unbtorsten commented 2 years ago

Programming flash is done by reprogramming the FPGA as a flash programmer. I am not aware of whether there is an existing open source technique we can use for this

Xilinx discusses this idea and use of a fallback/golden image here: https://www.xilinx.com/support/documentation/application_notes/xapp1247-multiboot-spi.pdf. Wouldn't it be sufficient to implement a reference "golden" image that handles the IPROG command etc.?!

Edit: @jrrk2 openFPGALoader's documentation mentions the -f flag to write to flash. Is this an option here?

jrrk2 commented 2 years ago

As an interim measure we could use a bitstream built with Vivado, but the end goal would be to build the bitstream with open source tools. This would make it compatible with Debian licensing where opaque binary blobs are discouraged.

rwhitby commented 2 years ago

Programming flash is done by reprogramming the FPGA as a flash programmer. I am not aware of whether there is an existing open source technique we can use for this

Xilinx discusses this idea and use of a fallback/golden image here: https://www.xilinx.com/support/documentation/application_notes/xapp1247-multiboot-spi.pdf. Wouldn't it be sufficient to implement a reference "golden" image that handles the IPROG command etc.?!

Edit: @jrrk2 openFPGALoader's documentation mentions the -f flag to write to flash. Is this an option here?

That is exactly the option I am investigating, see the notes above in my previous reply.

rwhitby commented 2 years ago

Genesys2 does not require any adaptor, the Digilent USB2JTAG sub-module is on board already. RAM programming may readily be done with:
openFPGALoader --cable digilent --bitstream blinky.bit --ftdi-channel 1
Programming flash is done by reprogramming the FPGA as a flash programmer. I am not aware of whether there is an existing open source technique we can use for this

I believe spiOverJtag as noted is that open source technique.

rwhitby commented 2 years ago

As an interim measure we could use a bitstream built with Vivado, but the end goal would be to build the bitstream with open source tools. This would make it compatible with Debian licensing where opaque binary blobs are discouraged.

Are the existing spiOverJtag bitstreams in openFPGAloader distributed on Debian? The intention is to continue to use the same spiOverJtag technique and just add a bitstream for the K7-325T.

rwhitby commented 2 years ago

Some progress:

rwhitby@inxs build % ./openFPGALoader -b qmtechKintex7 -c tigard --dump-flash --file-size 0x1000 foo.bin
Board qmtechKintex7 has not default cable
Jtag frequency : requested 6.00MHz   -> real 6.00MHz
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
Detail:
Jedec ID          : 01
memory type       : 60
memory capacity   : 19
EDID + CFD length : ff
EDID              : ffff
CFD               :
dump flash (May take time)
Open dump file DONE
Read flash : [==================================================] 100.00%
Done
rwhitby@inxs build % hexdump foo.bin
0000000 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
*
0000020 00 00 00 bb 11 22 00 44 ff ff ff ff ff ff ff ff
0000030 aa 99 55 66 20 00 00 00 30 03 e0 01 00 00 02 6b
0000040 30 00 80 01 00 00 00 12 20 00 00 00 30 02 20 01
0000050 00 00 00 00 30 02 00 01 00 00 00 00 30 00 80 01
0000060 00 00 00 00 20 00 00 00 30 00 80 01 00 00 00 07
0000070 20 00 00 00 20 00 00 00 30 02 60 01 00 00 00 00
0000080 30 01 20 01 02 00 3f e5 30 01 c0 01 00 00 00 00
0000090 30 01 80 01 03 65 10 93 30 00 80 01 00 00 00 09
00000a0 20 00 00 00 30 00 c0 01 00 00 04 01 30 00 a0 01
00000b0 00 00 05 01 30 00 c0 01 00 00 00 00 30 03 00 01
00000c0 00 00 00 00 20 00 00 00 20 00 00 00 20 00 00 00
00000d0 20 00 00 00 20 00 00 00 20 00 00 00 20 00 00 00
00000e0 20 00 00 00 30 00 20 01 00 00 00 00 30 00 80 01
00000f0 00 00 00 01 20 00 00 00 30 00 40 00 50 2b a5 20
0000100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
0001000

rwhitby commented 2 years ago

I now seem to be able to write a .mcs file using openFPGAloader and the spiOverJtag bitstream I created for the K7-325T:

rwhitby@inxs build % ./openFPGALoader -b qmtechKintex7 -c tigard -f led_top.mcs
write to flash
Board qmtechKintex7 has not default cable
Jtag frequency : requested 6.00MHz   -> real 6.00MHz
Open file DONE
Parse file DONE
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
Detail:
Jedec ID          : 01
memory type       : 60
memory capacity   : 19
EDID + CFD length : ff
EDID              : ffff
CFD               :
flash chip unknown: use basic protection detection
Erasing: [==================================================] 100.00%
Done
Writing: [==================================================] 100.00%
Done
rwhitby@inxs build %

hansfbaier commented 2 years ago

Well done! Great work!

rwhitby commented 2 years ago

Now to add this information to openFPGA so that it can recognise the flash chip correctly.

jrrk2 commented 2 years ago

Great work, I will try it. Excuse my ignorance, but how do you generate the MCS file without using Vivado?

rwhitby commented 2 years ago

Great work, I will try it. Excuse my ignorance, but how do you generate the MCS file without using Vivado?

At the moment, I'm using Vivado to generate the spiOverJtag bitstream (only has to be done once, and then submitted to openFPGAloader distribution) and also for the led_top.mcs (this is the software demo from the QMTech github repository).

I believe there is a way of generating MCS without requiring a Vivado license, but that's an item for further investigation.

rwhitby commented 2 years ago

Can someone check this addition to spiFlashdb.hpp against the data sheet to make sure I haven't made any mistakes?

https://www.infineon.com/dgdl/Infineon-S25FL256L_S25FL128L_256-MB_(32-MB)_128-MB_(16-MB)_3.0_V_FL-L_FLASH_MEMORY-DataSheet-v09_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ed40e335224

unbtorsten commented 2 years ago

I believe there is a way of generating MCS without requiring a Vivado license, but that's an item for further investigation.

@rwhitby @jrrk2: There is a report near the lower half of https://digilent.com/reference/learn/programmable-logic/tutorials/htsspisf/start on how to do this. However: why would I want to generate a MCS file which is specific to Xilinx? I would think that openFPGALoader can accept a BIN file?

rwhitby commented 2 years ago

However: why would I want to generate a MCS file which is specific to Xilinx? I would think that openFPGALoader can accept a BIN file?

Indeed it can:

rwhitby@inxs build % ./openFPGALoader -v -b qmtechKintex7 -c tigard --verify -f led_top.mcs
write to flash
Board qmtechKintex7 has not default cable
Jtag frequency : requested 6.00MHz   -> real 6.00MHz
found 1 devices
index 0:
    idcode 0x3651093
    manufacturer xilinx
    family kintex7
    model  xc7k325t
    irlength 6
File type : mcs
Open file DONE
Parse file DONE
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
1 60 19 ff read 16019ff
Detected: spansion S25FL256L 512 sectors size: 256Mb
RDSR : 00
WIP  : 0
WEL  : 0
BP   : 0
TB   : 0
SRWD : 0
00000000 00000000 00000000 00
Erasing: [==================================================] 100.00%
Done
Writing: [==================================================] 100.00%
Done
Verifying write (May take time)
Read flash : [==================================================] 100.00%
Done

rwhitby@inxs build % ./openFPGALoader -v -b qmtechKintex7 -c tigard --dump-flash --file-size 0x1000000 flash.bin
Board qmtechKintex7 has not default cable
Jtag frequency : requested 6.00MHz   -> real 6.00MHz
found 1 devices
index 0:
    idcode 0x3651093
    manufacturer xilinx
    family kintex7
    model  xc7k325t
    irlength 6
File type : bin
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
1 60 19 ff read 16019ff
Detected: spansion S25FL256L 512 sectors size: 256Mb
dump flash (May take time)
Open dump file DONE
Read flash : [==================================================] 100.00%
Done

rwhitby@inxs build % ./openFPGALoader -v -b qmtechKintex7 -c tigard --verify -f flash.bin
write to flash
Board qmtechKintex7 has not default cable
Jtag frequency : requested 6.00MHz   -> real 6.00MHz
found 1 devices
index 0:
    idcode 0x3651093
    manufacturer xilinx
    family kintex7
    model  xc7k325t
    irlength 6
File type : bin
Open file DONE
Parse file DONE
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7k325t.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
1 60 19 ff read 16019ff
Detected: spansion S25FL256L 512 sectors size: 256Mb
RDSR : 00
WIP  : 0
WEL  : 0
BP   : 0
TB   : 0
SRWD : 0
00000000 00000000 00000000 00
Erasing: [==================================================] 100.00%
Done
Writing: [==================================================] 100.00%
Done
Verifying write (May take time)
Read flash : [==================================================] 100.00%
Done

unbtorsten commented 2 years ago

Can someone check this addition to spiFlashdb.hpp against the data sheet to make sure I haven't made any mistakes? https://www.infineon.com/dgdl/Infineon-S25FL256L_S25FL128L_256-MB_(32-MB)_128-MB_(16-MB)_3.0_V_FL-L_FLASH_MEMORY-DataSheet-v09_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ed40e335224

You define the vendor ID as 0x016019. I suggest to use 0x00016019 to make it more explicit, cf. table 51 in the datasheet. I'm not sure where/how to check the remaining information?

rwhitby commented 2 years ago

The previous two devices in the table have the same format, so I followed the existing style.

rwhitby commented 2 years ago

This is now available for testing at https://github.com/rwhitby/openFPGALoader/tree/qmtechKintex7

unbtorsten commented 2 years ago

The previous two devices in the table have the same format, so I followed the existing style.

I understand. However, I have not been able to locate the bp/tb offsets in the datasheet. Did you adapt those from the other entries as well?

rwhitby commented 2 years ago

The previous two devices in the table have the same format, so I followed the existing style.

I understand. However, I have not been able to locate the bp/tb offsets in the datasheet. Did you adapt those from the other entries as well?

Those values are determined specifically from the status register layout:

rwhitby commented 2 years ago

Support for qmtechKintex7 board is now upstreamed in openFPGALoader.

jrrk2 commented 2 years ago

I tried your latest executable on Genesys2, and this is the result:

jonathan@nuc:~/xc7k325t-picosoc-nextpnr$ openFPGALoader --board qmtechKintex7 --cable digilent --bitstream picosoc.bit --ftdi-channel 1 -f
write to flash
Board qmtechKintex7 has not default cable
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7k325tffg676.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
Detail: 
Jedec ID          : 01
memory type       : 02
memory capacity   : 19
EDID + CFD length : 4d
EDID              : 8001
CFD               : 
flash chip unknown: use basic protection detection
Erasing: [==================================================] 100.00%
Done
Writing: [==================================================] 100.00%
Done
jonathan@nuc:~/xc7k325t-picosoc-nextpnr$

After apparently succeeding the board powers uo and sits there for a much longer period than normal (perhaps 20 secs), before declaring the DONE signal. After that the LEDs flash and the picosoc boots up:

Command> Booting..
Press ENTER to continue..
Press ENTER to continue..
Press ENTER to continue..
Press ENTER to continue..

  ____  _          ____         ____
 |  _ \(_) ___ ___/ ___|  ___  / ___|
 | |_) | |/ __/ _ \___ \ / _ \| |
 |  __/| | (_| (_) |__) | (_) | |___
 |_|   |_|\___\___/____/ \___/ \____|

   [9] Run simplistic benchmark

Command> 9
Cycles: 0x00161dd3
Instns: 0x0003df2d
Chksum: 0x5b8eb866

   [9] Run simplistic benchmark

Command> 
Command> 
`

So it's life captain, but not as we know it. I'm quite happy to make any necessary changes to achieve optimum performance, given a bit of guidance from you. Given the above, I feel justified in reopening the issue as well as congratulating you for the bonus behaviour.

rwhitby commented 2 years ago

Yes, we'll need to add an entry for the SPI flash chip, as it is unrecognised.

unbtorsten commented 2 years ago

Digilent's Genesys2 uses a xc7k325tffg900-2 with S25FL256S, cf. Section 6.2 of https://digilent.com/reference/_media/reference/programmable-logic/genesys-2/genesys2_rm.pdf

Datasheet for this SPI memory: https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17

I understand that a new entry needs to be added to spiFlashdb.hpp with the vendor ID that may be read from the table replicated below. The lower three bytes would then be 0x190201? However, I have yet to understand how to determine the remaining parameters. @rwhitby can you help, please?

trabucayre commented 2 years ago

I have added this chip. Now you will be able to have a correct display, but for basic usage (write somewhere into the flash) an entry is not really required.

rwhitby commented 2 years ago

I now have access to a Genesys2 board for a short time, so should be able to test this and also Makefile updates.

jrrk2 commented 2 years ago

I put in a pull request that works on my board, did you see it yet? EDIT: PR Reference: https://github.com/trabucayre/openFPGALoader/pull/180

unbtorsten commented 2 years ago

I second jrrk's pull request for openFPGALoader. However, I notice that the bitstream is only configured as expected immediately after programming. The FPGA does not seem to load it from flash after power cycling. Are we missing something in the configuration of the memory?

jrrk2 commented 2 years ago

How long did you wait?. The Vivado programming tool seems to generate a flash contents that take just a few seconds to configure, whereas openFPGAloader generated images take around 30s. That is a mystery, but it is an optimisation, not a failure (though I was taken by surprise the first time).

hansemro commented 2 years ago

On kc705, I also have to wait around 30 seconds after powering on to load the image.

unbtorsten commented 2 years ago

Duh, my bad. I noticed that the blinky-nextpnr Makefile does not write to flash: https://github.com/kintex-chatter/xc7k325t-blinky-nextpnr/blob/main/Makefile#L13 I'll continue discussion and updates at https://github.com/trabucayre/openFPGALoader/pull/180

unbtorsten commented 2 years ago

https://github.com/trabucayre/openFPGALoader/pull/180 has been merged. Hence, openFPGALoader now supports QMTech as well as Genesys2 boards.

Application examples for Genesys2

Load bitstream to SRAM: openFPGALoader -b genesys2 blinky.bit or openFPGALoader --cable digilent --ftdi-channel 1
Load bitstream to flash: openFPGALoader -b genesys2 --verify -f blinky.bit
Reset FPGA: openFPGALoader -b genesys2 -r

openXC7 / xc7k325t-blinky-nextpnr

openFPGAloader support #14