Open unbtorsten opened 2 years ago
Further input for reference:
At the same time, in order to speed up the FPGA loading the mcs file in QSPI Flash after power-on, we can configure the bit file to 4-wire mode (provided that your hardware must support 4-wire mode), and modify the loaded clock frequency to greatly speed up the FPGA The startup speed.
Configuring the bitstream with the constraint
set_property CONFIG_MODE SPIx4 [current_design]
and generating it by use of Vivado seems to be equivalent to generating a binary as mentioned above:
write_cfgmem -format bin -size 32 -interface SPIx4 -loadbit "up 0x00000000 $bitfile" -file "$binfile"
Either file (bitstream or binary) can be programmed by use of openFPGALoader with the commands
openFPGALoader -b genesys -f image.bit
openFPGALoader -b genesys -f image.bin
and yield short (not delayed) boot up times.
That’s good, but do we know what’s different between the x4 bitstream and the x1 bitstream in terms of fasm statements?
That’s good, but do we know what’s different between the x4 bitstream and the x1 bitstream in terms of fasm statements?
I have not looked into that aspect. Just wanted to point out that this seems to be something that is/can be engraved into the bitstream configuration (and not just a binary stream).
As per this command, we can see the quad mode is introduced during conversion from bitstream to binfile/mcsfile. So this is where we need to look to gain performance, rather than in the spiOverJtag Vivado settings
Originally posted by @unbtorsten and @jrrk2 in https://github.com/trabucayre/openFPGALoader/issues/181#issuecomment-1048059514