Genesys2 failure diagnostics

[jrrk2]

If nextpnr is run with the ffg900 variant, and the QMTECH constraints, it works. This might be because the QMTECH constraints just happen to be confined to the IOB_X0 block:

Info: Constraining 'clk' to site 'IOB_X0Y126' Info: Constraining 'led' to site 'IOB_X0Y114'

whereas the Genesys2 constraints are not:

Info: Constraining 'clk' to site 'IOB_X1Y24' Info: Constraining 'led' to site 'IOB_X0Y127'

Unfortunately I haven't been able to find a combination of clocks and LEDs that are on the IOB_X0 block only. However there can be no objection to the LED mapping which is almost the same as QMTECH.

The suggestion would be to try an internal ring oscillator as the next step to flush out any other issues.

[jrrk2]

https://caslab.csl.yale.edu/publications/burgiel2021characterization.pdf

[jrrk2]

This design appears to be suitable:

module blinky(
    inout clkio,
    output led
    );

    wire clko;
    wire clki = ~clko;

    reg [24:0] count = 0;

    always @ (posedge(clko)) count <= count + 1;

    assign led = count[24];

   // IOBUF: Single-ended Bi-directional Buffer
   //        All devices
   // Xilinx HDL Language Template, version 2020.2

   IOBUF #(
      .DRIVE(12), // Specify the output drive strength
      .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE" 
      .IOSTANDARD("DEFAULT"), // Specify the I/O standard
      .SLEW("SLOW") // Specify the output slew rate
   ) IOBUF_inst (
      .O(clko),     // Buffer output
      .IO(clkio),     // Buffer inout port (connect directly to top-level port)
      .I(clki),     // Buffer input
      .T(1'b0)      // 3-state enable input, high=input, low=output
   );

   // End of IOBUF_inst instantiation

endmodule

[jrrk2]

and we can try a fairly free choice of constraints such as:

set_property LOC F22 [get_ports clkio]
set_property IOSTANDARD LVCMOS18 [get_ports {clkio}]

set_property LOC T28 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports {led}]

resulting in the following allocation:

Info: Constraining 'clkio' to site 'IOB_X0Y281' Info: Constraining 'led' to site 'IOB_X0Y127'

ergo, we have constrained both pins to IOB_X0

[jrrk2]

I have tried the new blinky.v in Vivado on the Genesys2, and it is a happy bunny.

[jrrk2]

I have tried the nextpnr generated bitstream on the Genesys2, and it doesn't work, not a happy bunny.

[jrrk2]

The next stage is to invoke the magic converter to read the nextpnr bitstream back into Vivado, and run a DRC.

[jrrk2]

Implementation saved in branch ring-oscillator

[jrrk2]

ring-oscillator does not work yet. Clocking from a limited number of external pins (none of them official clock pins) is possible. 8-bit counter with manual clocking is operational.