openrisc orpsoc-cores issues

openrisc / orpsoc-cores

Core description files for FuseSoC

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issues

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Added SPI, cleaned up changes from orpsocv2 and tweaked .gitignore

#21 hansfbaier closed 10 years ago
2
cores/simple_spi: added

#20 hansfbaier closed 10 years ago
0
core additions

#19 skristiansson closed 10 years ago
1
Small fixes for the de0 nano system

#18 skristiansson closed 10 years ago
2
For upstream

#17 fjullien closed 11 years ago
1
systems: add Altera de1 board support

#16 fjullien closed 11 years ago
2
wb_avalon_bridge: wb burst to avalon pipeline access translation

#15 skristiansson closed 11 years ago
1
cores: uart16550: fix wb registered feedback access

#14 fjullien closed 11 years ago
3
cores: updates fixes and additions

#13 skristiansson closed 11 years ago
1
cores: adv_debug_sys: For X to zero during sim in crc module

#12 fjullien closed 11 years ago
2
cores: mt48lc16m16a2: change MEM_SIZES to lower case in patch 0004

#11 fjullien closed 11 years ago
1
cores: mt48lc16m16a2: core is now fetched from micron's url

#10 fjullien closed 11 years ago
2
Kill local versions of altera_virtual_jtag core

#9 skristiansson closed 11 years ago
1
cores: mt48lc16m16a2: core is now fetched from micron's url

#8 fjullien closed 11 years ago
0
systems: add minimal de0 nano board support

#7 skristiansson closed 11 years ago
1
wb_intercon_gen instantiation template

#6 skristiansson closed 11 years ago
1
cores: updates and additions

#5 skristiansson closed 11 years ago
1
cores: add simple 8-bit gpio core

#4 skristiansson closed 11 years ago
2
wb_intercon: replace rdt/sdt with wb spec compliant name (dat)

#3 skristiansson closed 11 years ago
1
cores: update mor1kx.core files

#2 skristiansson closed 11 years ago
0
My contribution to orpsocv3 ;)

#1 fjullien closed 11 years ago
0