Closed salmansheikh closed 4 years ago
Yep, that's exactly how I've been using it!
I've been using LiteX (https://github.com/enjoy-digital/litex) + LiteDRAM (https://github.com/enjoy-digital/litedram). This makes it easy to create a Vexriscv + Memory Mapped DDR3 memory controller + cache.
I'll be publishing an example of how this all works.
Cool thanks.
You mention 0.2 going under a short production run soon. Does that mean you will be willing to sell assembled boards? I could make pcbs but soldering those bga and other chips at home is a challenge to say the least.
Ahh, yes.
You can now join a groupbuy for boards here: https://groupgets.com/campaigns/710-orangecrab The boards will be fully assembled by a assembly house in the US.
That's a little pricey..
On Tue, Mar 24, 2020 at 7:09 PM Gregory Davill notifications@github.com wrote:
Ahh, yes.
You can now join a groupbuy for boards here: https://groupgets.com/campaigns/710-orangecrab The boards will be fully assembled by a assembly house in the US.
— You are receiving this because you modified the open/close state. Reply to this email directly, view it on GitHub https://github.com/gregdavill/OrangeCrab/issues/17#issuecomment-603551096, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAZFYMEIKKAOISG7EWNKGBLRJE4RZANCNFSM4LSGNSCQ .
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Do you think this board/FPGA could fit a RISC-V and a memory controller to use the 128MB memory?