search

orangecrab-fpga / orangecrab-hardware

ECP5 breakout board in a feather physical format
Other
477 stars 55 forks source link

UDQS/LDQS nets are switched on the SDRAM #24

Open benvanik opened 4 years ago

benvanik commented 4 years ago

I noticed these two differential signals were swapped in the r0.2 schematic. I've never done a DDR design and was wondering if there was a reason for this or if it snuck in during layout?

image

gregdavill commented 4 years ago

Yes, they were switched to improve routing, You'll notice that Upper Data (UDM, UDQS) is actually paired with D0-D7 bits on the FPGA end.

Ideally these nets should be renamed, to match what they're actually connected to.

krystian-hebel commented 7 months ago

DQSs are connected properly (although signal name is wrong), but DMs are not. As a result, when bytes are written one at a time and read back in group of 4 bytes, they are swapped. We discovered this in this function, with debug lines added - recv is the data from PRINT_GETC() and signature is what the function returns:

Awaiting neorv32_exe.bin...
recv: 0x000000fe
recv: 0x000000ca
recv: 0x00000088
recv: 0x00000047
signature: 0x8847feca

ERR_EXE

The problem is somewhat hidden with cache enabled, because all accesses are at least 4 bytes long in that case.