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orangecrab-fpga / orangecrab-hardware

ECP5 breakout board in a feather physical format
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DDR3 Routing Issue #46

Closed TheAnimatrix closed 2 years ago

TheAnimatrix commented 2 years ago

I haven't tested the DDR3 functionality on my board but as a person who does pcb design from time to time i couldn't help but notice a few things

  1. UDQS routed with D0-D7 (apparently switched in schematic so nvm)
  2. Address lines are randomly split between top and middle layers whilst maintaining the same length, microstrip on top would travel faster though wouldn't it ? so shouldn't the top layer routes be a tad longer considering this and the fact that they don't even need vias, or is this within spec ? (25 mils or 0.6mm ?? i'm sure just a couple vias would account for that)

I'll add more as i learn more about the same. If you have any good resources for ddr3 routing guidelines do share if possible. Thanks!

gregdavill commented 2 years ago

  1. The DQS pins are swapped. This was a mistake when I switched the D0-D7 and D8-D15 for better routing.

  2. This is correct. Simply not enough room to route all the signals on the same layer and maintain decent spacing and length match. Signals on outer layers will travel at different speeds than inner layers. But at the distances and speeds the ECP5 can operate the DDR3 at this is all easily within spec.

Here is some back of the envelope calculations if you're interested: 

150 pS / in for Microstrip,  or 180 pS / in for Stripline.

Typical Address Trace lengths: 15.1mm.
Outer traces 89ps, inner: 107ps, delta 18ps.
Max frequency of ECP5 DDR3 I/O 800MT/s (1250ps per transition.)

18/1250ps = 1.4%

Micron's design guides recommend length matching down to ~10% of the UI.