When you can't quite find the development board you want, why not make your own?
This project aims to design a feature rich FPGA development board that is compatible with the open source FPGA synthesis tools such as yosys, NextPNR and SymbiFlow, while also targeting larger logic designs that need faster IO. The requirements set out for this board are, in order of priority:
The ultimate objective of this board is to instantiate a soft core processor, such as the RISC-V, and use it to boot a Linux operating system with networking.
To that effect, this board is designed to be mechanically and electrically compatible with the Beaglebone Black, but featuring a Lattice ECP5 FPGA, which is available in logic sizes up to 85k LUTs, and a selection of hardware blocks for DDR3 DQS acceleration, MIPI interfaces, DSPs and 3Gbps SERDES.
The major features of this board include:
This project has completed the PCB layout phase, and we are moving into hardware prototyping. While we wait for the first boards to arrive, we have a schematic and some renders of the board that might satisfy your curiosity.
We would be happy to accept any feedback and review on the design that you might be willing to provide.
Copyright Owen Kirby 2020
This documentation describes Open Hardware and is licensed under the CERN OHL v1.2.
You may redistribute and modify this documentation under the terms of the CERN OHL v1.2. (see LICENSE.txt). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable conditions.