Fixed Latching for HardwarePWM

[mlehnhoff]

• removed unnessasary Register manipulations
• fixed "LPC_PWM1->LER = util::bit_value(0);" with "LPC_PWM1->LER |= util::bit_value(0);"
• fixed unneccessary offset of the period (e.g. "LPC_PWM1->MR0 = period - 1;"). Therefor the two workarounds in set_match() are not needed anymore

[descipher]

I'm quite certain the only change needed here is to set the latch in set_match. e.g. LPC_PWM1->LER = util::bitset_value(0, pin_has_pwm(pin)); // Enable Latch for MR0 and MRn channel No hardware available ATM to test it.

pin_has_pwm(pin) should return the pwm channel from 1 to 6 based on what I see. use bitset_value instead of bit_value, bitset_value applies with |=, bit_value returns only the bit position value so it's not optimum here. If the latch is set with 1 it will only work for MR1. MR0 rarely changes but should be latched .. not likely to see that issue unless the period is changed which would be almost never, but best to change it. @p3p Chris are you still maintaining the code?

[p3p]

@descipher Just enabling latching will reintroduce the more serious issue that the duty cycle is not always updated as it should be, I spent a long time trying to debug that when I "temporarily" disabled latching originally, it appeared to be caused by the duty cycle being updated multiple times per period, although that shouldn't be a problem.

I will need to find time to look at it again, although at this point I'm less familiar with this MCUs PWM peripheral than I was at the time.

[descipher]

Ok, thanks for the update. I did note that there were other people seeing odd behaviours on nxp community. I have a board coming, will have some time to poke at it. Just as a note the NXP user guide details that once you set the timer in PWM mode you must use the latch register to update any match value change.

[p3p]

Merged with #46