search

parasgidd / avsdpll_3v3

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
Apache License 2.0
15 stars 6 forks source link

issues

Newest
Newest Most commented Recently updated Oldest Least commented Least recently updated