Question about RTLtest

[Shainisore]

Hello, I noticed in the paper it is mentioned OpenCGRA will read control signal for simulation at RTL, but I didn't find the relevent code in CGRARTL_test.py in the test folder and was a little bit confused about how to load the control signal to start RTL simulation. It would be nice if you could provide some hint about this.

Thanks in advance!

[tancheng]

Hi, Here is an example to show how to provide the control signals to a target CGRA design. And you can run this test to see the simulation output. Each control signal item basically indicates the computation and routing direction that happens at each cycle on a tile.

Let me know if you have any other questions.

[Shainisore]

Thank you for the reply. Recently I have been trying to test out the generated verilog code using modelsim and there is something seems confusing. I was using the 2x2 cgra that was generated using the file in translation folder. I set (0,0) to do a load_const and load the memory and constant manually. It appears in the flexiblefurtl module the signal fu_send_out_msg which is from memunit cannot reach flexiblefurtl's send_out_msg output port. I traced down the signals and it seems this transfer depends recv_data_rdy from the tile under it and recv_in_rdy signal from memunit which is always 0 if executing ld_const. Also the tmpvarupdate_signal_in_dir in crossbar is a single signal instead of being a bundle of signals with the size as the outport. I don't quite understand those three thing. Could there be anything I missed during setup and anything I failed to grasp?

Thanks again for your time.

[tancheng]

Thanks for trying out the test. flexiblefurtl's send_out_msg depends on recv signals in general. But when it is ld_const, it should only depends on recv_opt. __tmpvar__update_signal_in_dir is only used as an intermediate variable to represent recv_opt__msg.outport[i] to indicate which inport should go to which outport. However, I never tried feed const (use ld_const) for RTL test. Are you trying to use the systolic test case for the generated CGRARTL? I actually don't have a const queue for RTL (there is one for CL though). Can you share how to set up your test case in detail? I can try to set it up in our env.

[Shainisore]

I think I misconfiged something during testing. I will try change my setting first and see if there is still problem. Thanks a lot for the reply!

[Shainisore]

I just tried to load the control signal of FIR to a 4x4 cgra. In my testbench I assigned data memory to {5,1,0} for all 100 entries. I also assigned the element__recv_const__msg of : tile 6 to {1,1,0}, which would be used by (8)add to increment the variable i in the target loop tile 10 to {3,1,0}, which would be used by (9)icmp as the variable NTAPS in the target loop tile 5 to {10,1,0}, which would be used by (2)getelementptr as the constant that should be added tile 9 to {0,1,0}, which would be used by (4)getelementptr as the constant that should be added

Those should be the same as the setting from CGRACL_FIR_demo_test.py. But it appeared to be not working. Is there any chance you could share a script that can generate the verilog file that is compatible with the FIR kernel?

Also it appears no signal is driving element__recv_const__msg in the tile. That is the reason I assigned it a value manually.

I also attached the testbench I am using.https://github.com/Shainisore/OpenCGRA_FIR_test/blob/main/tb.v

The script the verilog code was from https://github.com/Shainisore/OpenCGRA_FIR_test/blob/main/CGRARTL_test.py

Thank you

[tancheng]

Hi, thanks for the effort~! How about setting the element__recv_const__en as 1 in the tiles who perform LD_CONST. The problem is for the RTL model, I didn't provide ConstQueue (I only provide this for CL model) to each tile, so the recv_const will never be enabled and data will never be sent out. Please let me know if you can see any data sent out and any corresponding computation is done after the change. If that is the reason, I will try to include the ConstQueue into the RTL model.

[Shainisore]

I did that last time, this allows the memunit element to send out data but fusend_out__en is not drived to 1 as expect which prevent data to be sent out of fuRTL. I change send_ctrlen = send_ctrl__rdy to send_ctrl__en = 1 in ctrlmem so data can be sent out of fuRTL but it appears it cannot reach tiles send_out_msg port. The crossbar sets msg's bypass to 0 thus it cannot pass the channel to reach tiles' output. In general I think something is off in the crossbar. In the FIR test, the 6th tile((0)phi) is also not put msg in senddata[2] which will be directed to tiles output to the left. Crossbar's senddata[4] does have the messge though. I will check again regarding the crossbar. Speaking of which it seems CL test's msgs don't have the bypass bit? Thanks again for your support. I would really appreciate if you can provide the verilog of the cgra that can compute the FIR test.

[tancheng]

I am looking into this and will try to make your case work by the end of this week.

[tancheng]

Hi @Shainisore Sorry for the delay. I have made some changes to make the RTL model connect with ConstQueue. I also provided a RTL test for FIR kernel. You can pull the latest repo to generate the updated RTL code. It worked in the pytest, please let me know if there is anything doesn't work in your ModelSim.

[Shainisore]

Thanks so much. I will make sure to check it out asap.