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pothosware
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PothosZynq
DMA source and sink blocks for Xilinx Zynq FPGAs
https://github.com/pothosware/PothosZynq/wiki
Boost Software License 1.0
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Check dma_set_coherent_mask() before dma_zalloc_coherent() to fix allocation with 4.14+ kernels
#6
bychek
closed
4 years ago
0
Source/Sink for ADC/DAC interface
#5
ujinijoshi
opened
4 years ago
1
DMA Performance
#4
austinsteamboat
opened
8 years ago
1
FPGA logic to create tuser from stat/ctrl user data
#3
guruofquality
opened
9 years ago
0
user driver needs generic access to SG user fields
#2
guruofquality
opened
9 years ago
0
pzdud_release/acquire need to deal with start/end flags
#1
guruofquality
opened
9 years ago
0