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pphilippos
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simodense
Simodense: a RISC-V softcore for custom SIMD instructions
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Extending the number of Vector Registers
#3
HakamAtassi
opened
1 year ago
6
Updated byte address and automated firmware gen into testbench.v
#2
HakamAtassi
closed
1 year ago
0
cpu.v concat typo.
#1
sushakam
closed
1 year ago
9