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pranjalchanda08
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slash-sim
Slash Sim is a simple C based RV32 Instruction set simulator. This can be used to simulate any binary file that is compiled using RISCV toolchain.
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Release v0.1
#14
pranjalchanda08
opened
2 hours ago
0
ELF loading added
#13
pranjalchanda08
closed
2 hours ago
0
Add unique exit-code statuses
#12
shibcreate
opened
3 hours ago
0
Add [M] support for rv32IM
#11
shibcreate
opened
3 hours ago
2
ELF loading added
#10
pranjalchanda08
closed
3 hours ago
0
CSR support
#9
deveshshevde
opened
13 hours ago
0
Human readable reg dump success
#8
pranjalchanda08
closed
22 hours ago
2
Add human-readable output for context-registers dump
#7
shibcreate
closed
22 hours ago
0
Workflow
#6
pranjalchanda08
closed
2 days ago
0
Folder structure changes
#5
pranjalchanda08
closed
2 days ago
0
Add CSR instruction and register support
#4
pranjalchanda08
opened
2 days ago
0
Add Debugging interface
#3
pranjalchanda08
opened
2 days ago
0
Integrate ELF reader
#2
pranjalchanda08
closed
3 hours ago
0
Decode framework
#1
pranjalchanda08
closed
3 days ago
0