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psuggate
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axi-ddr3-lite
AXI DDR3 SDRAM Memory Controller for Xilinx GoWin Altera Intel Lattice FPGAs, written in Verilog.
MIT License
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hello. i am interesting with the project. but module "ulpi_bulk_axis" is not found.thanks
#1
allrighteveryday
opened
4 months ago
2