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rahulk29
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sram22
A configurable SRAM generator
BSD 3-Clause "New" or "Revised" License
41
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control logic layout
#466
rahulk29
closed
1 hour ago
0
Lint fixes
#465
rohanku
closed
1 day ago
0
add buffer chains to SRAM schematic
#464
rahulk29
closed
2 days ago
0
Column peripherals LVS/DRC
#463
rohanku
closed
1 day ago
0
add split vias to tgate mux cent tile
#462
rahulk29
closed
2 days ago
0
make outline consistent across tgate mux cells
#461
rahulk29
closed
2 days ago
0
add OUTLINE layer to tgate mux cells
#460
rahulk29
closed
3 days ago
0
tgate mux layout
#459
rahulk29
closed
5 days ago
0
Decoder folding, sense amp, and write driver layouts
#458
rohanku
closed
4 days ago
0
delay wlen start
#457
rahulk29
closed
1 week ago
0
New column peripherals
#456
rohanku
closed
1 week ago
0
Control logic updates
#455
rohanku
closed
1 week ago
0
correctly join simulation thread handles for sram simulation
#454
rohanku
closed
1 week ago
0
Sram fixes
#453
rohanku
opened
2 weeks ago
0
implement decoder sizing logic
#452
rahulk29
closed
1 week ago
0
Project questions w.r.t SKY 130 tapeout
#451
c-93
opened
5 months ago
2
fix: add SKY 130 submodule information
#450
rohanku
closed
8 months ago
0
fix: mention Substrate's SKY 130 PDK fork in README
#449
rohanku
closed
8 months ago
0
fix: update README parameters
#448
rohanku
closed
8 months ago
0
fix: README inaccurately stated number of columns
#447
rahulk29
closed
10 months ago
0
Bump rustix from 0.37.20 to 0.37.25
#446
dependabot[bot]
closed
8 months ago
0
How do I generate a dual port sram ?
#445
lu0de
opened
12 months ago
1
Fail to generate layout. "assertion failed: nx >= 0 && ny >= 0"
#444
lu0de
closed
8 months ago
4
Hstrap cell fixes
#443
rohanku
opened
1 year ago
0
Generate fake delay line lib
#442
rahulk29
closed
1 year ago
0
Generate fake TDC lib
#441
rahulk29
closed
1 year ago
0
Generate abstracts (LEFs) for test site SRAMs
#440
rahulk29
closed
1 year ago
0
Optimize control logic v2
#439
rahulk29
closed
1 year ago
0
Run PEX on SRAMs in sram22::main
#438
rahulk29
closed
1 year ago
0
Generate delay line abstract view (LEF)
#437
rahulk29
closed
1 year ago
0
Run PEX on the delay line
#436
rahulk29
closed
1 year ago
0
Run PEX on the TDCs
#435
rahulk29
closed
1 year ago
0
Test Chip Doc Updates
#434
rohanku
closed
1 year ago
0
Add TDC verilog model and abstract generation code
#433
rahulk29
closed
1 year ago
0
Update docs for SRAM control signals
#432
rahulk29
closed
1 year ago
0
SRAM test ports
#431
rohanku
closed
1 year ago
0
Generate LEF/LIB for Rocket SRAM macros
#430
rahulk29
closed
1 year ago
0
Fine TDC cell layout
#429
rahulk29
closed
1 year ago
0
Tunable Delay Line
#428
rohanku
closed
1 year ago
0
Fine TDC first pass layout
#427
rahulk29
closed
1 year ago
0
Allow non-power-of-two SRAM sizes
#426
rahulk29
opened
1 year ago
0
Change X to RAND in `test_chip.md`
#425
rahulk29
closed
1 year ago
0
Top Level LVS
#424
rohanku
closed
1 year ago
0
Shared BIST across all SRAM test macros
#423
rahulk29
closed
1 year ago
0
SRAM timing analysis chip documentation
#422
rahulk29
closed
1 year ago
0
Optimize control logic
#421
rahulk29
closed
1 year ago
0
Basic BIST RTL (Incomplete)
#420
rohanku
closed
1 year ago
0
Add coarse TDC schematic and testbench
#419
rahulk29
closed
1 year ago
0
BIST RTL
#418
rohanku
closed
1 year ago
0
Run formatter
#417
rahulk29
closed
1 year ago
0
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