HiZ inputs to rggen_default_register

[kraxi1730]

Hello,

If a register implements fewer bits than the bus width, then some portion of input signals, i_bit_field_value and i_bit_filed_read_data, to rggen_default_register are HiZs.

To avoid this, could rggen be updated to pass the correct width(sum of bit_field widths) to DATA_WIDTH parameter instead if setting that parameter to BUS_WIDTH? Would that have any other side effects and cause functional issues?

[taichi-ishitani]

Hi @kraxi1730 ,

Thank you for opening this issue!

some portion of input signals, i_bit_field_value and i_bit_filed_read_data, to rggen_default_register are HiZs

These unconnected HiZ bits are masked and are not used. Therefore you don't need to fix.

https://github.com/rggen/rggen-verilog-rtl/blob/1dbbbf7c6a8cc9aa258f50cbfcd3d4a1f4b77c97/rggen_register_common.v#L124 https://github.com/rggen/rggen-verilog-rtl/blob/1dbbbf7c6a8cc9aa258f50cbfcd3d4a1f4b77c97/rggen_register_common.v#L131

[taichi-ishitani]

@kraxi1730 Can you close this issue if you have no further topics?

[kraxi1730]

Thanks for the response.

Maybe you could consider this request in a future revision so that generated RTL is "clean" for simulation/synthesis and other post-processing tools.