This is an sample testbench to demonstrate integrating UVM RAL model generated by RgGen
into UVM based testbench.
This env uses flgen to generate *.f files which are given to simulator tools. Therefore, you need to install the tool before using this env. See its repository for details.
In this testbech, CSR modules generated by RgGen
are used as DUT and there are three types of DUT:
This testbench inclues three sample testcases invoking pre-defined test sequences.
Test Name | Test Sequence |
---|---|
ral_hw_reset_test | uvm_reg_hw_reset_seq |
ral_bit_bash_test | uvm_reg_bit_bash_seq |
ral_access_test | uvm_reg_access_seq |
This testbench depends on some submodules so you need to get them from GitHub repositries. To do this, hit the command below on the root of this repositly.
$ cd rggen-sample-testbench
$ ./setup_submodules.sh
If execution of above commands failed you need to get them from GitHub repositlies directly and set some environment variables.
$ git clone https://github.com/taichi-ishitani/tue.git
$ export TUE_HOME=`pwd`/tue
$ git clone https://github.com/taichi-ishitani/tvip-common.git
$ export TVIP_COMMON_HOME=`pwd`/tvip-common
$ git clone https://github.com/taichi-ishitani/tvip-apb.git
$ export TVIP_APB_HOME=`pwd`/tvip-apb
$ git clone https://github.com/taichi-ishitani/tvip-axi.git
$ export TVIP_APB_HOME=`pwd`/tvip-axi
$ git clone https://github.com/rggen/rggen-sv-rtl.git
$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-rtl
$ git clone https://github.com/rggen/rggen-sv-ral.git
$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-ral
$ git clone https://github.com/rggen/rggen-verilog-rtl.git
$ export RGGEN_VERILOG_RTL_ROOT=`pwd`/rggen-verilog-rtl
$ git clone https://github.com/rggen/rggen-vhdl-rtl.git
$ export RGGEN_VHDL_RTL_ROOT=`pwd`/rggen-vhdl-rtl
Synopsys VCS simulator and Cadence Xcelium simulator are supported.
Move to the work directry
sim/apb/systemverilog
sim/apb/verilog
sim/apb/vhdl
sim/axi4lite/systemverilog
sim/axi4lite/verilog
sim/axi4lite/vhdl
sim/wishbone/systemverilog
sim/wishbone/verilog
sim/wishbone/vhdl
Hit make
command on the work directry
$ make
By default, all sample testcases will be execluted by VCS simulator. If you want to use Xcelium or Vivado simulator, add SIMULATOR
option to makefile
command.
$ make SIMULATOR=xcelium
$ make SIMULATOR=dsim
$ make SIMULATOR=vivado
If you want to execute an specific testcase then you need to give its name to make
command like below.
$ make ral_bit_bash_test
The GUI
option is to enable the inteructive debug environment.
To invoke the GUI frontend, give this option to make
command like below.
$ make ral_bit_bash_test GUI=dve
$ make ral_bit_bash_test GUI=verdi
$ make ral_bit_bash_test SIMULATOR=xcelium GUI=indago
$ make ral_bit_bash_test SIMULATOR=vivado GUI=on
You can post your questions, feedbacks, bug reports, etc. by using following ways.
Copyright © 2019-2024 Taichi Ishitani. This testbench is licensed under the MIT License, see LICENSE for futher detils.