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### Check for existing issues
- [X] Completed
### Language
VHDL
### Tree Sitter parser link
https://github.com/jpt13653903/tree-sitter-vhdl
### Language server link
https://github.com/VHDL-LS/r…
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VHDL_LS extension requires a file listing the files to consider for VHDL language parsing. It should be easy to generate this file given the information given to GHDL for building the simulation.
Use…
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Would be nice to have a VHDL linter additionally.
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**Description**
When reworking GHDLs pipeline (see #2718), it was found that backend `llvm-jit` has failing tests for MinGW64 and UCRT64.
MinGW64: https://github.com/Paebbels/ghdl/actions/runs/104…
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Is their is a way to see report statment and the current state by name. Because cxxrtl ignore the report statment and convert all state into binary.
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I am trying to understand if there is a way to write data to VHDL signals from Python in **runtime**. This could also be possible if message passing can be done between Python and VHDL, about which …
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Right now, we are using a two-step setup for Synopsys VCS which according to http://www.vlsiip.com/vcs/ is limited to Verilog only. VCS(-MX) is capable of simulating VHDL too with a three-step process…
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When the `spinal.core.formal.GlobalClock()` is used, an invalid name is given to the signal in VHDL.
Which generates with VHDL to:
```vhdl
signal _global_clk : std_logic;
attribute gclk of _global…
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**Is your feature request related to a problem? Please describe.**
In the CircuirtVerse we have only a Module export to the Verilog description language.
**Describe the solution you'd like**
The …