Can use VCS

[jamesningd]

I use VCS to run this testbench. I use command : make , in directory "rggen-sample-testbench-master/sim/apb/verilog"

But I have error as following:

make sim_vcs TEST=ral_hw_reset_test make[1]: Entering directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog' [ -f simv ] || make compile_vcs make[2]: Entering directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog' vlogan -full64 -sverilog -timescale=1ns/1ps -ntb_opts uvm-1.2 -l vlogan_uvm.log

Warning-[MXIR-W] VCS-MX build is required Please make sure that vlogan is from the intended build.

                     Chronologic VCS (TM)
   Version O-2018.09-SP2_Full64 -- Thu Aug 24 13:32:38 2023
           Copyright (c) 1991-2018 by Synopsys Inc.
                     ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure.

Error-[ILWOR] Incorrect Logical Worklib or Reflib The incorrect logical lib is "work".
Please check your Synopsys setup file.

CPU time: .110 seconds to compile make[2]: [/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/vcs.mk:69: compile_vcs] Error 255 make[2]: Leaving directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog' make[1]: [/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/vcs.mk:64: sim_vcs] Error 2 make[1]: Leaving directory '/home/jamesning/work/reggen/rggen-sample-testbench-master/sim/apb/verilog' make: *** [makefile:32: ral_hw_reset_test] Error 2

Would you please help me to fix the bug?

[taichi-ishitani]

I also use VCS but I've never seen such error. I think you need to check your environment according to this message.

Error-[ILWOR] Incorrect Logical Worklib or Reflib
The incorrect logical lib is "work".
Please check your Synopsys setup file.