Error : uninitialized virtual interface object in rggen_ral_backdoor_pkg

[Tejoyadav]

Hi, I'm using the rggen generated models for our design and verification.

And I'm using AXI interface, for which I'm using AXI VIP for verification. when I'm trying to start uvm_reg_access_seq I'm getting the following error.

the corresponding line is:

Please help me in solving this issue..

Thanks.

Regards, Tejoyadav

[taichi-ishitani]

Is this error happened on your TB?

[taichi-ishitani]

The uvm_reg_access_seq is using the backdoor access feature. Please see the wiki document below to enable the backdoor access feature. https://github.com/rggen/rggen/wiki/Use-Generated-RTL-Modules-and-RAL-Models#backdoor-access

[Tejoyadav]

Yeah, I have referred this, I already given +define+RGGEN_ENABLE_BACKDOOR in run command and also set my hdl path

[taichi-ishitani]

You need to check the given HDL path is correct or not at first. To do this, set a breakpoint to the code below and check whether or not the path variable is showing correct HDL path. https://github.com/rggen/rggen-sv-ral/blob/727da7c095f380a46dfc9d14a171ed6d1d2383e1/rggen_ral_backdoor_pkg.sv#L69

[Tejoyadav]

yeah I displayed the path variable, using $display it is showing: test_top.DUT.csr_inst.lpddr5mc_reg_file_inst.g_addr_map_1.u_register.u_register_common.u_backdoor

[taichi-ishitani]

Is there an instnce of the rggen_backdoor module on this path? https://github.com/rggen/rggen-sv-rtl/blob/master/rggen_backdoor.sv

[Tejoyadav]

Don't know exactly, untill this point "test_top.DUT.csr_inst.lpddr5mc_reg_file_inst" I'm setting through the hdl_path setting, rest is getting added by the tool itself.

[taichi-ishitani]

Can you share your compile log file?

[Tejoyadav]

It's in company server, it is not possible to share the file. But, I can share the screenshots of the instances you want.

[taichi-ishitani]

Ok, I understand. I think you're using VCS. Which compile flow are you using? 2 step flow or 3 step flow?

[Tejoyadav]

2 step flow

[taichi-ishitani]

Did you define the RGGEN_ENABLE_BACKDOOR macro by using +define+ compile switch?

[Tejoyadav]

Yeah, I did

[taichi-ishitani]

Are generated RTL modules also compiled by this command?

[Tejoyadav]

yes, they are

[taichi-ishitani]

I cannot find any problem on your compile command for now.

---

The VIF is given from an instance of the rggen_backdoor module. I think this module is not instantiated on the above HDL path so this error is happened. I'd like you to dump wave file and check the module is instantiated on the path.

[taichi-ishitani]

Can you tell me revison hash of rggen-sv-ral which you're using?

[Tejoyadav]

Currently I don't have, I'm just using the copied version from my peer. I can tell you that by tomorrow.

[taichi-ishitani]

I think you change the rggen_ral_backdoor_pkg.sv file. Can you provide the file which you change?

[Tejoyadav]

[Tejoyadav]

This is how I'm setting the hdl path. Is this way is correct or should I use add_hdl_path_slice method.

[taichi-ishitani]

Is this way is correct or should I use add_hdl_path_slice method.

Yes, this is correct way.

[taichi-ishitani]

The VIF is given from an instance of the rggen_backdoor module. I think this module is not instantiated on the above HDL path so this error is happened. I'd like you to dump wave file and check the module is instantiated on the path.

How about this?

[Tejoyadav]

The VIF is given from an instance of the rggen_backdoor module. I think this module is not instantiated on the above HDL path so this error is happened. I'd like you to dump wave file and check the module is instantiated on the path.

How about this?

u_backddor is the instance of that rggen_backdoor module

[Tejoyadav]

Can you tell me revison hash of rggen-sv-ral which you're using?

727da7c

[taichi-ishitani]

Module instances are OK.

[taichi-ishitani]

"test_top.DUT.csr_inst.lpddr5mc_reg_file_inst"

Is this valid path to the generated CSR module?

[Tejoyadav]

yeah, it is working fine when I'm starting uvm_reg_hw_reset_seq

[taichi-ishitani]

uvm_reg_hw_reset_seq does not use backdoor access so this error is not happened. You can copy the HDL path from DVE's Hierarchy window.

I'd like you to compare the HDL path which you specified and path copied from the Hierarchy window.

[Tejoyadav]

test_top.DUT.csr_inst.lpddr5mc_reg_file_inst.g_addr_map_1.u_register.u_register_common.u_backdoor

[taichi-ishitani]

HDL path is OK.

[taichi-ishitani]

I have not use the generated CSR modules and RAL models with VCS's partition compile feature so I'm not sure this combination works fine. Can you remove option switches related to partition compile and try again?

[Tejoyadav]

I have not use the generated CSR modules and RAL models with VCS's partition compile feature so I'm not sure this combination works fine. Can you remove option switches related to partition compile and try again?

I tried by removing partcomp switch, still it is giving the same error.

[taichi-ishitani]

https://github.com/rggen/rggen-sv-rtl/blob/b3fcdd239d556fb99b86c0a0133f30e85809be61/rggen_backdoor_pkg.sv#L19

Can you put a breakpoint to the above line and check whether or not the vif variable is empty?

[taichi-ishitani]

Did you change the rggen_backdoor.sv file? https://github.com/rggen/rggen-sv-rtl/blob/master/rggen_backdoor.sv

If yes, can you provide your changed one?

[Tejoyadav]

I tried this way, but only the first display is getting printed.

[taichi-ishitani]

can you change this line $display(vif[hdl_path]); like below and try again?

foreach (vif[i]) begin
  $display("hdl path: %s", i);
end

[Tejoyadav]

This display statements I'm getting, for all the registers.

[taichi-ishitani]

thanks, I understand the reason. Can you change the HDL path given to the set_hdl_path_root method to small case?

[Tejoyadav]

yeah, that issue got resolved.

Thankyou.

One more thing I want to confirm, this uvm_info is getting printed for every register. Is this fine or I will get any info statements telling that "read and mirrored values are matched" ?

Also, pls tell why that upper case name is creating issue..

[taichi-ishitani]

Is this fine or I will get any info statements telling that "read and mirrored values are matched" ?

Yes, it's fine. This message notifies a verification sequence is starting.

Also, pls tell why that upper case name is creating issue..

The HDL path to the instance of rggen_backdoor module is used as an access key to the VIF. The given HDL path is normalized and changed to lower case when storing the VIF. https://github.com/rggen/rggen-sv-rtl/blob/b3fcdd239d556fb99b86c0a0133f30e85809be61/rggen_backdoor_pkg.sv#L48 Therefore, you need to give lower case name to the set_hdl_path_root method.