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riscv / riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard
https://jira.riscv.org/browse/RVG-94
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Is hardware breakpoint exception the only way for native debug? #1086

Open zhangdujiao opened 1 day ago

zhangdujiao commented 1 day ago

From 1.4. Background, "The optional Trigger Module provides features that are useful for native debug". The native debugger can debug a program by access the csr (icount, itrigger, etc.) to set a hardware breakpoint (action=0), is this the only way for native debugger? Can native debugger set the software breakpoint by adding ebreak to initial program? Or, Can native debugger have the access with other Debug Module to debug? (suppose there are many DMs in the SoC)

zhangdujiao commented 1 day ago

Since native debugger to debug the program by accessing the csrs of Trigger Module. So, for the SMP SoC, the native debugger can only debug the program running in itself rather than any other cores, right?