riscv riscv-v-spec issues

riscv / riscv-v-spec

Working draft of the proposed RISC-V V vector extension

https://jira.riscv.org/browse/RVG-122

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issues

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example of vmv.v.* is inconsistent with the definition in spec-1.0.pdf?

#947 Oxyw opened 6 months ago
3
README needs to reflect that the 1.0 vector spec has been ratified

#946 camel-cdr closed 3 weeks ago
1
Spec PDF does not have PDF TOC

#945 algrobman opened 7 months ago
0
Mask instruction tail elements behavior issue(while vl=0)

#944 TogashiHan closed 7 months ago
2
what's the vd of vcompress in case of vl =0

#943 Kou66666 closed 7 months ago
5
wha

#942 Kou66666 closed 7 months ago
0
Add clarification regarding supported index value of indexed load/stores

#941 troibe closed 8 months ago
1
The behavior of slideup/slidedown when i is 0

#940 SoufSilence closed 8 months ago
4
Specify all vector CSR widths and vtype.vill behavior when XLEN changes

#939 aswaterman closed 8 months ago
0
Are the vector registers required to have a consistent state at reset?

#938 michael-platzer closed 7 months ago
4
vmv.s.x/vfmv.s.f behavior question

#937 EventScheduler closed 8 months ago
2
Is vxsat raised based on pre-round or post-route result for vnclip?

#936 liangkaiwang closed 9 months ago
3
Signed averaging addition through vaadd

#935 sun-jacobi opened 9 months ago
3
Rounding increment is unclear when d equals to 0

#934 sun-jacobi opened 9 months ago
3
Question about '... traps on ... instructions are always reported with a vstart of 0 ...'

#933 YenHaoChen closed 9 months ago
11
What is the destination value beyond the tail for compare instruction under tail agnostic?

#932 larryrong opened 9 months ago
1
Question about the vl when using element groups.

#931 JerryShih closed 10 months ago
4
README should reflect that rvv has been ratified

#930 camel-cdr opened 10 months ago
1
Should I unroll the loop in implementation of vvadd?

#929 sunnycase closed 10 months ago
14
load mask with immediate value

#928 howjmay opened 11 months ago
1
Update toolchain link

#927 lianakoleva opened 11 months ago
0
Main README dead link

#926 lianakoleva closed 11 months ago
3
Question about vsrl instruction in RVV spec

#925 LWenH closed 11 months ago
11
vstart and precise abort for chaining case

#924 jeremyccl opened 11 months ago
3
Note: conflict with subword (byte) AMO

#923 a4lg closed 11 months ago
1
[Question] Possibility of some math API like i/l/llrint Vectorization

#922 Incarnation-p-lee closed 11 months ago
5
Propose a PF/AF optional subset for long-vector implmentation

#921 sequencer opened 1 year ago
3
pdf is probably too big (uncompressed)

#920 jnk0le opened 1 year ago
0
Rotate and shift vector mask bits

#919 camel-cdr closed 1 year ago
2
Issue in Constraints on Setting vl

#918 latifbhatti closed 1 year ago
4
Clarify slide semantics

#917 nick-knight closed 6 months ago
7
What does "PoR" mean?

#916 tianhu-zeng closed 1 year ago
2
Fix error in description for vslide1up

#915 eopXD closed 1 year ago
0
benchmarks for RVV

#914 wanghuibin0 opened 1 year ago
2
is vsetdcfg deprecated?

#913 wanghuibin0 closed 1 year ago
2
Checks ordering: nop vs trap

#912 ajayvreddy opened 1 year ago
0
Proposal: Make `Zvfh` to depend on `Zvfhmin` instead of `Zve32f`

#911 a4lg opened 1 year ago
0
Specification status updates

#910 a4lg closed 1 year ago
0
Clarify Zicsr dependence

#909 nick-knight closed 1 year ago
0
Post-Ratification Clarification: Dependency from `Zve32x` to `Zicsr`

#908 a4lg closed 1 year ago
5
If vtype.vill=1, is VLMAX equal to 0? If vlamx=0, then any value configured for vstart is treated as an illegal instruction, because in this case, any vstart value is greater than the element index.

#907 Wei-VV1995 opened 1 year ago
1
[question] Does V extension implies F and D?

#906 WojciechMula opened 1 year ago
4
vsetvli/vsetivli encoding

#905 jrahmeh closed 1 year ago
2
When the value of vstart written through the csr instruction is greater than the vlmax under the current configuration, whether the hardware can be treated as an illegal instruction to implement

#904 Wei-VV1995 closed 1 year ago
4
When vstart is not 0, is the execution of the vset{i}vl{i} command handled according to the illegal command exception?

#903 Wei-VV1995 closed 1 year ago
3
What happens if VLMAX ends up less than 1?

#902 benjaminou4412 opened 1 year ago
2
Clarify that compares only AND in the mask if vd == v0

#901 michael-platzer closed 1 year ago
10
Compares effectively AND in the mask under a mask-undisturbed policy

#900 michael-platzer closed 1 year ago
5
Question about Narrowing Floating-Point/Integer Type-Convert Instructions

#899 bhbruce closed 1 year ago
2
Behavior of masked fault-only-first loads

#898 dzaima closed 1 year ago
4