Closed reo-pon closed 4 years ago
This PR adds support for synthesizing RSD on Vivado only. The previous method, synthesis using a Synplify netlist, can also be used.
This PR assumes using Vivado 2019.2, so please use this version.
The procedure flow for synthesis is almost the same as previously, except not using synplify netlist (so you don't need Synplify for synthesizing RSD!) Please see the wiki page below describes if you want to synthesis RSD and run on Zedboard. https://github.com/rsd-devel/rsd/wiki/en-fpga-zynq-build-linux-simple (in English) https://github.com/rsd-devel/rsd/wiki/jp-fpga-zynq-build-linux-simple (in Japanese)
This PR adds support for synthesizing RSD on Vivado only. The previous method, synthesis using a Synplify netlist, can also be used.
This PR assumes using Vivado 2019.2, so please use this version.
The procedure flow for synthesis is almost the same as previously, except not using synplify netlist (so you don't need Synplify for synthesizing RSD!) Please see the wiki page below describes if you want to synthesis RSD and run on Zedboard. https://github.com/rsd-devel/rsd/wiki/en-fpga-zynq-build-linux-simple (in English) https://github.com/rsd-devel/rsd/wiki/jp-fpga-zynq-build-linux-simple (in Japanese)