RSD is a 32-bit RISC-V out-of-order superscalar processor core. RSD is very fast due to aggressive OoO features, while it is very compact and can be synthesized for small FPGAs. The key features of RSD are as follows:
Install the following software for running simulation.
Tested environment:
Refer to scripts in Processor/Tools/SetEnv.sh and set environment variables.
Go to Processor/Src and make as follows.
make # compile
make run # run simulation
make kanata # run simulation & outputs a konata log file
-f Makefile.verilator.mk
like make -f Makefile.verilator.mk run
-f Makefile.vivado.mk
like make -f Makefile.vivado.mk run
If the simulation ran successfully, you find "kanata.log" in Processor/Src.
You can see the execution pipeline of your simulation above with Konata.
Copyright 2019-2023 Ryota Shioya (shioya@ci.i.u-tokyo.ac.jp) and RSD contributors, see also CREDITS.md. This implementation is released under the Apache License, Version 2.0, see LICENSE for details. This implementation integrates third-party packages in accordance with the licenses presented in THIRD-PARTY-LICENSES.md.
Susumu Mashimo et al., "An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor", IEEE International Conference on Field-Programmable Technology (FPT), 2019. A pre-print version is here.