This PR adds an uncachable memory access support for RSD.
The rule of executing loads/stores on an uncachable memory region (e.g., memory-mapped IO) is changed as below:
Uncachable loads always receive data from a data bus. They never update cache.
Uncachable stores always write data directly to memory. They first receive data from the data bus in a cache line granularity, update the cache line, and then send it back to the data bus. They never update cache.
MSHRs play a key role as below:
Every uncachable load/store misses in cache and allocates an MSHR.
The MSHR issues a memory read request to the data bus in a cache line granularity.
A load receives data from the MSHR and deallocates it.
A store merges its data and the loaded cache line, and then the MSHR sends the merged data to the data bus.
Note:
The uncachable region is currently mapped to VAddr 0x8004_0000-0x8005_0000 and PAddr 0x0025_0000-0x0026_0000.
fence iorw, iorw must be executed before and after every uncachable load/store because of the following limitations. The current implementation does not guarantee that uncachable loads/stores are executed in program order. In addition, it does not prevent uncachable loads/stores from accessing data in StoreQueue and an MSHR that is allocated by a different load/store, resulting in the use of expired data.
This PR adds an uncachable memory access support for RSD. The rule of executing loads/stores on an uncachable memory region (e.g., memory-mapped IO) is changed as below:
MSHRs play a key role as below:
Note:
fence iorw, iorwmust be executed before and after every uncachable load/store because of the following limitations. The current implementation does not guarantee that uncachable loads/stores are executed in program order. In addition, it does not prevent uncachable loads/stores from accessing data in StoreQueue and an MSHR that is allocated by a different load/store, resulting in the use of expired data.