rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor
Apache License 2.0
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Add a cache flush feature #22

Closed msmssm closed 3 years ago

msmssm commented 3 years ago

This PR adds a feature to flush ICache and DCache on executing fence.i. This feature enables fence.i to guarantee that all writes to memory before this instruction are visible to ICache access after this instruction. In addition, fence.i can be used to trigger ICache and DCache flush by a programmer.

The flow to execute fence.i is as below.

  1. fence.i stalls in the rename stage until all the preceding ops are committed and all stores' data is written back to DCache.
  2. The fence.i enters the dispatch stage and all the following ops stall in the rename stage.
  3. When the fence.i is executed, it sends a cache flush request to CacheFlushManager and enters the ReplayQueue.
  4. CacheFlushManager makes ICache and DCache flush all data they have.
    • ICache resets all the valid bits of tagArray.
    • DCache writes all dirty cache lines to memory and resets tagArray, dirtyArray and dataArray.
  5. Once both ICache flush and DCache flush are completed, CacheFlushManager sends a completion signal to ReplayQueue and ReplayQueue issues the fence.i to the execution pipeline.
  6. Once the fence.i is re-executed and committed, the whole pipeline is flushed and the core starts to fetch the instruction behind the fence.i.