Any provision for secure coding?

rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor

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Any provision for secure coding? #34

Closed RaoShri closed 3 years ago

RaoShri commented 3 years ago

Hi, I was looking into security aspects of RISCV processors. Is there any provision for making a block of memory secure in rsd? Like TZPC for ARM? Regards, Shrinidhi

shioyadan commented 3 years ago

Hi RaoShri,

I missed this issue and I'm sorry for the late reply. RSD has a very simple static address translation and memory protection mechanism, but it does not have a more advanced security mechanism. We would like to prioritize the implementation of memory protection by the regular MMU first.