An illegal instruction exception should be raised when the shift amount of the shift instructions is 32 or more, as described in Chapter 4.2 of RISC-V User-Level ISA.
For RV32I, SLLI, SRLI, and SRAI generate an illegal instruction exception if imm[5] 6= 0.
For example, the following three instructions have a shift amount of 32 and are decoded as illegal instructions for RV32I.
Therefore, such instructions should raise an illegal instruction exception, but in the current RSD, such instructions are executed normally without raising an illegal instruction exception.
Steps to reproduce the issue
If you execute a code that embeds an invalid shift instruction like the code below, you can confirm that the illegal instruction executes normally without raising an illegal instruction exception.
int main(void){
asm volatile (".byte 0x13, 0x93, 0x02, 0x02");
}
Observed Behavior
An illegal instruction exception should be raised when the shift amount of the shift instructions is 32 or more, as described in Chapter 4.2 of RISC-V User-Level ISA.
For example, the following three instructions have a shift amount of 32 and are decoded as illegal instructions for RV32I.
Therefore, such instructions should raise an illegal instruction exception, but in the current RSD, such instructions are executed normally without raising an illegal instruction exception.
Steps to reproduce the issue
If you execute a code that embeds an invalid shift instruction like the code below, you can confirm that the illegal instruction executes normally without raising an illegal instruction exception.