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rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor
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About the reset cycle #42

Closed Ting199708 closed 3 years ago

Ting199708 commented 3 years ago

Hi,

I am the master student from National Cheng Kung University, Taiwan, and I'm interesting in your design but there are some problems about the reset cycle.

In ResetController.sv, the CYCLE_OF_RESET_SEQUENCE is set to 10000. Why we need so many cycles to reset the CPU? Is it related to FPGA simulation?

If I use Modelsim/Verilator to simulate and set the CYCLE_OF_RESET_SEQUENCE to a smaller number (e.g. 10), does it influence the simulation result?

Thank you!

shioyadan commented 3 years ago

Hi,

The CYCLE_OF_RESET_SEQUENCE is the time required for the state machines in the RSD to initialize each module. In particular, initializing the valid flags in the caches take a long time because they are initialized one entry per cycle. So it can influence the simulation result.

We may give too large a margin for the initialization, and 10000 cycles are probably too long. We know that using these fixed initialization cycles is a vulnerable design, and we will fix it in the future.