Vivado synth 8-659 : type mismatch in port association

[Jagannaths3]

Hi, I am trying to synthesize the rsd for Zynq zcu102 board. I have the following issues/observations 1) Main_Zynq_wrapper still uses SystemVerilog constructs - Worked around by writing two wrappers. 2) The RAM_Vivado.sv - DistributedMultiPortRAM is missing the ENTRY_NUM parameter 3) I get the synthesis error Eg. [Synth 8-659] type mismatch in port association: bit [5:0]A[0:0] vs. bit [3:0]B[0:0] () This happens on ports .wa and .ra of DistributedMultiPortRAM This is Xilinx recommendation - https://www.xilinx.com/support/answers/64034.html

However, I am trying to unpack the structure for every instance

Example : Before fixing (original)

DistributedMultiPortRAM #(
    .ENTRY_NUM( ISSUE_QUEUE_ENTRY_NUM ),
    .ENTRY_BIT_SIZE( $bits(Entry) ),
    .READ_NUM( WAKEUP_WIDTH ),
    .WRITE_NUM( DISPATCH_WIDTH )
) dstRAM (
    .clk( port.clk ),
    .we( write ),
    .wa( writePtr_flat ),
    .wv( writeData ),
    .ra( readPtr_flat ),
    .rv( readData )
);

---

AFTER fixing

reg [$bits(IssueQueueIndexPath)+1:0] writePtr_flat[DISPATCH_WIDTH];
always_comb begin
    for(int i = 0; i < DISPATCH_WIDTH; i=i+1) begin
        writePtr_flat[i] = port.writePtr[i];
    end
end

reg [$bits(IssueQueueIndexPath)+1:0] readPtr_flat[WAKEUP_WIDTH];
always_comb begin
    for(int i = 0; i < WAKEUP_WIDTH; i=i+1) begin
        readPtr_flat[i] = readPtr[i];
    end
end

DistributedMultiPortRAM #(
    .ENTRY_NUM( ISSUE_QUEUE_ENTRY_NUM ),
    .ENTRY_BIT_SIZE( $bits(Entry) ),
    .READ_NUM( WAKEUP_WIDTH ),
    .WRITE_NUM( DISPATCH_WIDTH )
) dstRAM (
    .clk( port.clk ),
    .we( write ),
    //.wa( writePtr ),
    .wa( writePtr_flat ),
    .wv( writeData ),
    //.ra( readPtr ),
    .ra( readPtr_flat ),
    .rv( readData )
);

---

I fixed at multiple places but there are far too many. Is there a generic solution to avoid this manual hacking for Xilinx synthesis?

Thanks, Jagannath

[reo-pon]

Which version of Vivado do you use?

When I synthesized the rsd in 2019.1, this error did not appear. Please upgrade Vivado to 2019.1 or later and try to synthesize the rsd. (You will still get a little synthesis errors, but can easily fix it. We will fix this in later.)