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RSD: RISC-V Out-of-Order Superscalar Processor
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Error when run in verilator: no viable conversion from 'const VlWide<92>' to 'const uint32_t [92]' #72

Closed zhangkanqi closed 6 months ago

zhangkanqi commented 7 months ago

Hi!

When I run sudo make -f Makefile.verilator.mk, it reports errors:

clang++ -D RSD_FUNCTIONAL_SIMULATION_VERILATOR -D RSD_FUNCTIONAL_SIMULATION -D RSD_VERILATOR_TRACE -D RSD_MARCH_FP_PIPE -Wno-attributes -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-bool-operation -Wno-tautological-bitwise-compare -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Os -include limits -std=gnu++14 -Os -c -o TestMain.o ../../../Src/SysDeps/Verilator/TestMain.cpp In file included from ../../../Src/SysDeps/Verilator/TestMain.cpp:4: ../../../Src/SysDeps/Verilator/VerilatorHelper.h:482:5: error: no viable conversion from 'const VlWide<92>' to 'const uint32_t [92]' RSD_MAKE_DEBUG_REG_STAGE_ACCESSOR(DebugRegister, npReg, logic, valid); ^~~~~~~~~~~~~~~~~ ../../../Src/SysDeps/Verilator/VerilatorHelper.h:455:64: note: expanded from macro 'RSD_MAKE_DEBUG_REG_STAGEACCESSOR' i.member = h->DebugRegister##stage##_##member(r, index); \ ^ /usr/local/share/verilator/include/verilated_types.h:146:5: note: candidate function not viable: 'this' argument has type 'const VlWide<92>', but method is not marked const operator WDataOutP() { return &m_storage[0]; } // This also allows [] ^ /usr/local/share/verilator/include/verilated_types.h:147:5: note: candidate function operator WDataInP() const { return &m_storage[0]; } // This also allows [] ^ ./VMain_Zynq_Wrapper_VerilatorHelper.h:187:54: note: passing argument to parameter 'e' here bool DebugRegister_npReg_valid(const uint32_t (& e)[92], uint32_t i); ^ In file included from ../../../Src/SysDeps/Verilator/TestMain.cpp:4: ../../../Src/SysDeps/Verilator/VerilatorHelper.h:483:5: error: no viable conversion from 'const VlWide<92>' to 'const uint32_t [92]' RSD_MAKE_DEBUG_REG_STAGE_ACCESSOR(DebugRegister, npReg, OpSerial, sid); ^~~~~~~~~~~~~~~~~~ ../../../Src/SysDeps/Verilator/VerilatorHelper.h:455:64: note: expanded from macro 'RSD_MAKE_DEBUG_REG_STAGEACCESSOR' i.member = h->DebugRegister##stage##_##member(r, index); \ ^ /usr/local/share/verilator/include/verilated_types.h:146:5: note: candidate function not viable: 'this' argument has type 'const VlWide<92>', but method is not marked const operator WDataOutP() { return &m_storage[0]; } // This also allows [] ^ /usr/local/share/verilator/include/verilated_types.h:147:5: note: candidate function operator WDataInP() const { return &m_storage[0]; } // This also allows [] ^ ./VMain_Zynq_Wrapper_VerilatorHelper.h:186:56: note: passing argument to parameter 'e' here uint32_t DebugRegister_npReg_sid(const uint32_t (& e)[92], uint32_t i); ^ In file included from ../../../Src/SysDeps/Verilator/TestMain.cpp:4: ../../../Src/SysDeps/Verilator/VerilatorHelper.h:485:5: error: no viable conversion from 'const VlWide<92>' to 'const uint32_t [92]' RSD_MAKE_DEBUG_REG_STAGE_ACCESSOR(DebugRegister, ifReg, logic, valid); ^~~~~~~~~~~~~~~~~

I don't know why these errors occur. My environment configurations are as follows:

export RSD_ROOT=~/rsd
export RSD_GCC_PATH=/opt/riscv32/bin
export PATH=$PATH:$RSD_GCC_PATH
export RSD_GCC_PREFIX=riscv32-unknown-elf-
export RSD_VERILATOR_BIN=~/verilator/bin

Verilator version: v4.106

zhangkanqi@hwfuzz:~/rsd/Processor/Src$ verilator -V Verilator 4.106 2020-12-02 rev v4.106 Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See https://verilator.org for documentation Summary of configuration: Compiled in defaults if not in environment: SYSTEMC = SYSTEMC_ARCH = SYSTEMC_INCLUDE = SYSTEMC_LIBDIR = VERILATOR_ROOT = /usr/local/share/verilator SystemC system-wide = 0 Environment: MAKE = PERL = SYSTEMC = SYSTEMC_ARCH = SYSTEMC_INCLUDE = SYSTEMC_LIBDIR = VERILATOR_ROOT = /home/zhangkanqi/verilator VERILATOR_BIN = Features (based on environment or compiled-in support): SystemC found = 0

zhangkanqi@hwfuzz:~/rsd/Processor/Src$ /usr/local/bin/verilator --version Verilator 4.106 2020-12-02 rev v4.106

gcc version: 13.2.0

zhangkanqi@hwfuzz:~/rsd/Processor/Src$ riscv32-unknown-elf-gcc --version riscv32-unknown-elf-gcc (gc891d8dc23e) 13.2.0 Copyright (C) 2023 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

zhangkanqi commented 7 months ago

It requires version v4.026 of verilator exactly. Otherwise, it may report errors.

shioyadan commented 6 months ago

I'm sorry for my late response. We have recognized the issue you explained and are working to support the latest Verilator. However, our current implementation has caused a significant slowdown in the latest version, and resolving it will require more time. Thank you for your report.