Open zhangkanqi opened 5 months ago
Your point seems correct, and we forgot to include the FS and XS bits in the floating point extension implementation. We will implement the feature.
I'm sorry for my late response. I would like to mention that I work at a university in Japan, and currently, we are in one of the busiest periods of the year due to many important events, such as the thesis defense and some important examinations. This has significantly limited my time to check everything...
It's not late at all. Thank you for taking the time to confirm and reply. Btw, Happy Chinese New Year~
Currently, I do not have enough time to fix this issue. To ensure it is not forgotten, I have reopened it. Once the issue is resolved, I will close it again. Thank you!
Hi,
After runing instruction
csrs mstatus, a0
(a0=0x00007800) in rsd, mstatus is set to 0x00007800, not the expected value 0x80007800.According to the privilege specification of RISC-V, if FS=11, SD should be set to 1.
So I wonder is this a bug in rsd?