rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor
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[Bug Report] RSD doesn't update mstatus after `mret` instruction #76

Closed zhangkanqi closed 7 months ago

zhangkanqi commented 8 months ago

Bug Description:

The previous value of mstatus is 0x00007800, but after executing mret instruction, mstatus is still 0x00007800. However, according to the riscv specification as below, mstatus should be 0x80006080, which spike does so.

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zhangkanqi commented 8 months ago

Sorry, I forget that RSD merely supports M-mode. But what should RSD do when encounter mret instruction? Doing nothing?

shioyadan commented 7 months ago

Thank you for your report. After checking the specification, I found the following statement, which leads me to believe that the FS field should be updated by privileged code (software), and the SD should be updated by hardware according to the FS. Consequently, it appears that the hardware does not need to update the FS on the mret. Furthermore, the FS and SD have not been implemented yet and should be implemented.

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zhangkanqi commented 7 months ago

I see. Thanks for your reply:)