rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor
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[Bug Report] `fflags` records the accumulated status incorrectly #77

Closed zhangkanqi closed 1 month ago

zhangkanqi commented 5 months ago

Bug Description:

After a fcvt.wu.s instruction, fflags becomes 0x1. But then after a bltu instruction, fflags becomes 0x0.

I find the source code of RSD as follows(in CommitStage.sv):

`ifdef RSD_MARCH_FP_PIPE
        // CSR FFLAGS Update
        fflagsWE = FALSE;
        fflagsData = '0;
        for (int i = 0; i < COMMIT_WIDTH; i++) begin
            if (commit[i]) begin
                fflagsWE = TRUE;
                fflagsData |= activeList.fflagsData[i];
            end
        end
        csrUnit.fflagsWE = fflagsWE;
        csrUnit.fflagsData = fflagsData;
`endif

It seems that RSD wants to record the accumulated status of fflags. If so, fflags should be 0x1 after bltu instruction rather than 0x0.

I wonder if this is a bug? Thank u :)

shioyadan commented 5 months ago

Thank you for your report. After reviewing the specifications of the fflags, your point seems correct. The fflags should not be updated until the next FP instruction is executed. We will address this issue.