[Bug Report] `fflags.UF` is not set correctly after `fdiv.s` instruction

rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor

Apache License 2.0

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Closed zhangkanqi closed 4 months ago

zhangkanqi commented 4 months ago

Environment:

RSD version: bd7c5c12dfd8d20c7cb5c1d5a75f7ba59f9fce52

Bug Description:

There is an instruction fdiv.s fs3, fa5, fa4, where fa5=0x3292f14b and fa4=0x71da37da .

After the fdiv.s instruction, fflags.UF flag in RSD maintains 0 . However, fflags.UF flag in spike is set to 1 .

It seems that RSD updates fflags.UF incorrectly?

zhangkanqi commented 4 months ago

Updating of fflags isn't implemented yet.