[Bug Report] `fflags.DZ` set incorrectly after `fdiv.s` instruction

rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor

Apache License 2.0

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Closed zhangkanqi closed 1 month ago

zhangkanqi commented 1 month ago

Environment:

RSD version: bd7c5c12dfd8d20c7cb5c1d5a75f7ba59f9fce52

Bug Description:

There is an instruction fdiv.s fs1, fa4, ft7, where fa4=0x47bca361 and ft7=0x00000000.

After the fdiv.s instruction, fflags.DZ flag in RSD maintains 0 . However, fflags.DZ flag in spike is set to 1 .

It seems that RSD update fflags.DZ incorrectly.

zhangkanqi commented 1 month ago

Updating of fflags isn't implemented yet.

zhangkanqi commented 1 month ago

Hi, @lpha-z Does updating of fflags isn't implemented completely yet?

lpha-z commented 1 month ago

From what I can see, it does not appear to be implemented, but I don't know how it actually is. @ RSD team?