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rsd-devel / rsd

RSD: RISC-V Out-of-Order Superscalar Processor
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[Bug Report] Wrong sign bit when 0 is multiplied by a negative number #92

Open zhangkanqi opened 1 month ago

zhangkanqi commented 1 month ago

Environment:

RSD version: bd7c5c12dfd8d20c7cb5c1d5a75f7ba59f9fce52


Bug Description:

There is an instruction fmul.s ft9, fs4, ft8, where fs4=0x00000000 and ft8=0x998a3664.

After the fmul.s instruction, the result of ft9 in RSD is 0x00000000. However, the result in spike is 0x80000000.


It seems that RSD mistakes the sign bit of the final result?

lpha-z commented 1 month ago

Thank you for finding the bug.

@ RSD team: Fix the following 32'h00000000 to 32'h80000000. The identity element of floating-point addition is -0.0, not +0.0.

            if(fpuCode[i] == FC_MUL) begin
                fmaAddend[i] = 32'h00000000;
            end

https://github.com/rsd-devel/rsd/blob/master/Processor/Src/Pipeline/FPBackEnd/FPExecutionStage.sv#L180

zhangkanqi commented 1 month ago

Thanks for your confirmation!

lpha-z commented 1 month ago

We reopen this report because this bug has not been fixed yet. When we finish fixing, we will close this report.