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fpga
The USRP™ Hardware Driver FPGA Repository
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32 bit addition merges I and Q samples
#5
samprager
opened
6 years ago
3
pulseciravg fails for avg_size = 1
#4
samprager
closed
6 years ago
1
pulse_cir_avg block read back register typo [fixed]
#3
samprager
opened
6 years ago
0
Vivado cannot find/locate variables from noc_block_pulse_cir_avg.v file. Thus, the simulation window shows all signals as invalid or empty -- no waveform is generated.
#2
samprager
opened
6 years ago
2
Pulse cir avg - simulation issue thread
#1
samprager
opened
6 years ago
0