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scale-lab / OpenPhySyn

EDA physical synthesis optimization kit
https://woset-workshop.github.io/PDFs/2020/a09.pdf
BSD 3-Clause "New" or "Revised" License
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How do you load the parasitic information of the the design #6

Closed ganeshgore closed 4 years ago

ganeshgore commented 4 years ago

I have a pre-routed design which has a dummy inverter/buffer cells already placed. I want to optimize the sizing of these gates based to get the lowest latency possible. Does that look like the correct use of the OpenPhySym tool? I managed to get the tool running using docker and tried _buffer_fanouttransformation. I was wondering how to provide the parasitic information to the tool to get or does it calculated based on the tech.lef + def file provided?

ahmed-agiza commented 4 years ago

Hi @ganeshgore, thanks for your interest. The current approach relies on using an average wire parasitics estimation which is set using set_wire_rc to extract the average values from the given metal layer or set_wire_rc to give custom wire RC. The timing information is extracted from OpenSTA which supports read_spef command to feed parasitics information although we did not test this aspect so far. I also recommend using repair_timing command instead which is the most comprehensive command in the tool to perform various optimization (you can check the different options it supports in the README file. The tool performs different optimizations to meet the timing constraints and solving electrical violations, if you want to meet higher constraints you can try tightening the clock period. Let me know if anything is not clear, and feel free to open a suggestion ticket for features/enhancements that you think might be useful for your flow.