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sdnellen / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Apache License 2.0
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64bit register interface #22

Closed roowatt closed 3 years ago

roowatt commented 4 years ago

I am looking at setting default regwidth=64 and implement a 64bit register bank for a processor I am using.

When I set the regwidth=64 there are two additional signals added to the decoder, I can't find doco as to how these are to be hooked up, is there any?

The additoinal signals are shown below, how do I use them? h2d_pio_dec_trans_size d2h_dec_pio_trans_size

sdnellen commented 4 years ago

The interface allows access of different sized registers in the address space (max range is 1 to 16 times the min_data_size value). Default min_data_size is 32b, so in your case with a max reg width of 64b, 2 values are allowed (if all regs are same size, the input can be tied off). The d2h_dec_pio_trans_size output indicates the size of the register at the specified address and can be used to detect an error where say a 32b write is attempted on a 64b reg. See https://github.com/sdnellen/open-register-design-tool/wiki/SystemVerilog-IO-descriptions#parallel-processor-interface for more info.