sdnellen / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Apache License 2.0

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asic-design eda fpga-development register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm verilog

readme

open-register-design-tool

Ordt is a tool for automation of IC register definition and documentation. It currently supports 2 input formats:

SystemRDL - a stardard register description format released by Accellera.org
JSpec - a register description format used within Juniper Networks

The tool can generate several outputs from SystemRDL or JSpec, including:

SystemVerilog/Verilog RTL code description of registers
UVM model of the registers
C++ and python models of the registers
C header file providing register address and field defines
XML and text file register descriptions
SystemRDL and JSpec (conversion)

Easiest way to get started with ordt is to download a runnable jar from the Juniper repo release area. Ordt documentation can be found here.