-
https://github.com/Nitheeshkumar521/asic-design-class/blob/main/asiclab1image.jpeg
-
Hey Yuli,
I am gonna use this project through ASIC Design Approach, Do you have any Tips for me?
Like Did you decide the Clock frequency?, Did you have any cloudy logic that take more than one C…
-
### Feature Description
I'm interested in running designs through sc using standard commercial ASIC tools (in title).
## Steps Taken
* I did a few `grep -R` text searches on the repo looking…
-
# Description
You can use OpenLane2 to convert your Verilog file to a GDSII Layout file. You can refer to [this](https://openlane2.readthedocs.io/en/latest/)
# Notes:
- You are eligible to get br…
-
Hi,
I have read your recent journal but cannot really understand the step to do the GL test and get the output render frames. I am quite novice in the ASIC workflow.
To be able to do this test woul…
-
-
Hi all,
What are the minimum requirements of a SERV core to design a many-core ASIC using ASAP7 predictive PDK? I'm thinking about something like SMP architecture and I'm going to use [OpenSoC Fabric…
-
where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL
-
- As we consider SRAM22 for an asic design: Was SRAM22 already taped-out in SKY130 before?
- Would it be possible for external users, who have access to corresponding licenses (or open source tools…
c-93 updated
2 months ago
-
This was mentioned by @dpetrisko.
Apparently Vivado is failing to map wide FMAs to DSPs efficiently.
Lakeroad alone probably can't do this -- once a solver query needs to figure out that some co…