This is specifically for the circuit in Sequential Logic > Shift Registers > Parallel-In Serial-Out.
Here is what the circuit currently looks like:
The problem with this is the first input is unaffected by the load/shift input, causing the circuit to fill up with with a logic 1.
I added a mux in the front of the left most D flip-flop which seemed to have fixed the problem.
This is specifically for the circuit in Sequential Logic > Shift Registers > Parallel-In Serial-Out. Here is what the circuit currently looks like: The problem with this is the first input is unaffected by the load/shift input, causing the circuit to fill up with with a logic 1.
I added a mux in the front of the left most D flip-flop which seemed to have fixed the problem.