Feature request: Propagation Delay Setting

[HemQL]

Having a configurable propagation delay on logic gates would open a number of possible simulations and designs. Pipelining demonstrations, self-clocked flip-flop applications, and more. Either a global configurable value or a per-component parameter would be fantastic, allowing for more realistic logic simulation for ASIC/FPGA visualization.

[pfalstad]

For now, there's a Delay Buffer component which you can use to add delays in your logic circuits.