RISC-V: initial support for reading riscv-opcodes

[janvrany]

This PR introduces revamped support for RISC-V based on (official) riscv-opcodes. This requires modified RISC-V PDL introduced in commit 8e4d3b78.

As of now, support for extensions is limited (only RV64 base integer ISA and M extensions is supported) but still it's practical.

There's a lot to be desired, such as:

• support for pseudo instructions (j, ret, ...)
• full support for RV64G & RV32G ISAs
• CSRs
• support for .is_jump (to allow program analysis)

This will be added later when needed.