ISA Variant Granularity

[shingarov]

I was playing with code involving mtdbcr0 today, and I feel like our current ArchC language itself is prohibitively limited when it comes to ISA variants. Right now, on POWER we have two XLENs and two byte orders, and no further ability to distinguish between processors.

Consider, for example, SPR 0x134. On the Book E line, the 4xx, the A2* etc., this is DBCR0 but on something like POWER10 it's SPURR. Cf. binutils-gdb/opcodes/ppc-opc.c, see the BOOKE flag on mtdbcr0. Therefore, something like

    .machine ppc
main:
    mtdbcr0 3

gas will fail to assemble:

Error: unrecognized opcode: `mtdbcr0'

So we have to say

    .machine "440"

(and similarly when disassembling, pass -M 440 to objdump).

In ArchC, we can't even use "fields" because of mtcr but cr is not an SPR. So we would need a long list of extended mnemonics for mtspr, but not all of them are available on all processors, and we don't have a counterpart to ppc-opc.c's "FLAGS indicating which processors support the instruction" in ArchC.

[janvrany]

So we would need a long list of extended mnemonics for mtspr, but not all of them are available on all processors, and we don't have a counterpart to ppc-opc.c's "FLAGS indicating which processors support the instruction" in ArchC.

No, but we can have something like powerpc_isa_440.ac and powerpc64_isa_power10.ac and then do something like this in powerpc_440.ac

ARCH_CTOR(powerpc_440) {
       ac_isa("powerpc_isa.ac");
       ac_isa("powerpc_isa_440.ac");
};

In fact, we already do this kind of thing, see https://github.com/janvrany/Pharo-ArchC-PDL/blob/master/powerpc/powerpc64.ac#L45-L46

I'm not saying having something like binutils' flags / .archwould not be better - In fact, the solution above would be bit cumbersome to use with DSL assemblers. I'm happy to add support for flagging instructions / mnemonics with architecture variants.

Also note that this is issue is not POWER specific, you have the same "problem" with RISC-V (various profiles), with AArch64 (v8, v8.2, ...) and so on.