Zotino v1.1

[hartytp]

• [x] Remove simulations page from schematic (let's just leave the Spice files in the repository)
• [x] Update power budget
• [x] Use two output resistors in series/parallel to improve power handling (200mW short-circuit)
• [x] reverse C143, C145, C147, C84
• [x] mirrored SOT23 diode footprint due to Altium bug - part of component is on top layer, pads are on bottom layer.
• [x] add Shottky diodes at the LDO outputs
• [x] 3mm higher EMC shield on PSU
• [ ] hole for heatsink in EMC shield
• [x] reverse IDC connector on BNC to IDC board
• [ ] Zero-index all channels
• [x] swap BNC connector GND terminals
• [x] either add ~2mm plastic washers on BNC barrel behind front panel or move BNC connectors 2mm towards FP. This is to enable fixing the BNC connectors to the panel using the screws.
• [x] Please remove the annotation "This module connects to Kasli ..." and replace it with something like "EEM connector: IO are LVDS, I2C is 3V3 LVCMOS, P3V3_MP up to 20mA, P12V up to 1A." (use same annotation as other EEMs)
• [x] run PI and thermal simulations. Please can you also double check that all regulators can handle the required current etc. Please also double check the layout for any places that could cause issues (bad cross-talk or patristics that could lead to oscillation, etc)
• ~Can we run the digital interface from 2V5?~ No -- see sampler discussions about this!
• [x] Fix temperature controller issues:
• [x] Silk + schematic + panel should be "v1.x" not "rev1.x" Silk should just say "Zotino v1.1" (copy from Sampler) still needs doing: Add Zotino name to schematic and pcb, add version number to schematic and front panel
• [x] Only have one set of +-12V regulators, not two!
• [x] Reduce SMPs outputs slightly, since we're only using +-12 regulators
• [x] Remove BNC to IDC connectors from this; they should be a separate project (they are a useful adapter for other boards like Sampler, and not part of the DAC design).
• [x] Upload BNC to IDC connector boards as a separate project.
• [x] Update front panel (see discussion in other issues)
• [x] Let's remove the simulations page from the schematic, better to just include the simulation itself in the project directory
• [x] Tidy up adapter boards cf comments here (two posts). Add annotations on silk and schematic for the adapter boards indicating how the connectors map to the channel (e.g. top=0, bottom=1 for the BNCs etc).
• [x] Remaining temperature controller issues here
• [x] Add more test points for power supply rails (both at the SMPS and for the LDOs), SPI, etc
• [x] For the TEC IDC, let's add a ground wire between the TEC and the thermistor to reduce EMI from the noisy TEC current (which is rectified by the temperature sensor, leading to errors).

[dhslichter]

I would vote strongly for removal of the thermal island and instead using vias/ground planes to spread heat from the DAC and make it equilibrate better to the board. This ought to keep the DAC from running itself to death temp-wise, at least.

[hartytp]

@gkasprow Happy New Year!

Sorry to add to the huge to do list, but is there any chance we can put this in the pipeline to do asap?

This is very important to us because we don't currently have a version of this board that we can use for testing (the current version kills the DACs too quickly to be testable). So, I'd like to get a version with bug fixes sent to manufacture as soon as possible.

Hopefully these changes are small and will be quite quick to implement.

Obviously, crucial Sayma/RF PA issues (like the 1V8 diagnostics) should take priority.

[hartytp]

Greg, is there any chance we can get this sent off to manufacture this week? I'd really like to get this done so we can start testing properly.

For the temperature control stuff, here are my thoughts:

• Let's scrap the thermal island
• Add some way for users to mount a TEC. Do this however you think is best, but here is my initial thought (feel free to overrule)
  • Leave some exposed copper on the board's underside along with some mounting holes that can be used to attach a peltier and heat sink (I'm assuming that it's better to temperature control the ground that the DAC and reference connect to than to try to mount the TEC directly on the DAC, but feel free to do what you think is best here)
  • Run a thermal simulation to verify that a TEC which can drive +-3W into the thermal island is able to change the DAC's temperature by +-2C or so (that should be enough to ensure regulation in most lab conditions once the board has warmed up)
  • Users who want the best stability can attach a self-adhesive insulating strip over the DAC + reference on the top side of the board to scree out air currents
  • Add a 10k NTC SMT thermistor on the board's underside as close the the TEC as possible
  • Bring the 10k thermistor to a header on the top of the board. This header should ideally also connect to the TEC (are there any TECs that have SMT connections?). The header can then be used to connect this to an external temperature controller EEM via ribbon cable/IDC (see the Thermostat EEM page on the wiki for an idea of what this could look like)
  • Scrap all temperature controller related components on the PCB (including the LEDs)

How does that sound?

Thanks!

[hartytp]

Greg, thanks for posting the initial v1.1 schematics! Can you do me a favour, please and tick off the items you've addressed on the list at the top of this post (that will make my design review easier).

[hartytp]

Greg, I've checked over the schematic you uploaded and it mainly looks good. Apart from the outstanding issues above (I've ticked off the ones that looked fixed to me):

• Did you run thermal + PI simulations yet? In particular, I'd be interested to see how many C/W a peltier would produce here so that we know we can temperature stabilise this with a sensible TEC power.
• To match the peltier to the I/V rating of the proposed Thermistor EEM, I'm assuming the TEC we'll use will be something like this
  • What is the diameter of the holes you used for the TEC wires? Will they be wide enough for this kind of TEC? (I didn't see that specified on the data sheet)
  • [x] Please can you add an annotation on the schematic and silk screen for the polarity of the TEC wires ("TEC+" and "TEC-"). Please name the nets TEC+ and TEC- instead of B1 and B2
  • [x] The TEC wiring should be able to handle at least 2A with no problems (and without too much voltage drop in the wiring harness). Should we use 1 or 2 more pins for the TEC to ensure that's not a problem? Would it be worth alternating TEC+ and TEC- in the ribbon cable to reduce emission from the TEC current? (Or is that overkill?)
  • [x] Is the exposed copper area large enough to mount a 15mm x 15mm TEC?
• [x] After thinking about this more, let's remove the P12V0, P3V3_MP and I2C lines from the temperature controller header. They're not really necessary with the proposed temperature controller EEM design. (This presumably means we can remove the I2C extender from the design, which is nice!)
• [x] Do the cutouts you've left in around the DAC make any difference to the thermal management? Or, is it better to remove them completely?
• [x] Can you add a hole in the screening can for the TEC + heat sink?
• [x] would it make sense to design the heat sink mounting holes around some standard commercially available heat sink hole pattern. I'd like it if we don't have to machine the heat sink to make it work. We should also include a suggested heat sink PN in the schematic
• Are there any disadvantages of having the DAC on the underside of the PCB? I guess we already have quite a few components there, so this isn't a problem (won't make the board more expensive or more fragile than it already is).
• Since the DAC is on the underside of the PCB, there isn't room to add insulating foam on top of the DAC (unless one also adds a filler panel). That should be fine since the DAC's thermal paddle means it is very well heat sunk to the PCB, so small air fluctuations won't be too much of an issue (and we're only aiming for +-200mK or so stability, which isn't too tough to meet).

Other than that, looks good to me!

[hartytp]

Oh, one other thing: let's wait and see what @cjbe's measurements tell us about the noise on Zotino v1.0 before doing anything about this, but...

The SMPS we're currently using has over current protection, but not over voltage or over temperature protection AFAICT. I wonder if it's a little fragile, and if some of the abuse we've given it could have lead to the SMPS failing on some of our boards?

[hartytp]

@gkasprow IIRC, for cross-talk testing, we were planning to build a trivial board which breaks out a HD68 to 4 x IDCs. Did we ever do that? I can't find it in the repository. If not, is it possible to do that for Zotino v1.1? Thanks!

[gkasprow]

@hartytp The HD68 to IDC and IDC to BNC adapters were added to repo

[hartytp]

Thanks!

[hartytp]

@gkasprow I had a quick look at Zotino v1.0 to try to track down the remaining noise issue. Configuration:

• DAC removed
• OpAmp input is grounded
• Looking at noise on the DAC outputs and on the power supply using an audio frequency analyzer.

I did not get to the bottom of it. However, given how much abuse these boards have had, I suspect that something may just be damaged. At this stage, I don't think there is any point debugging these boards further. Let's just go to the next design revision, please!

[a-shafir]

How about separate with beads the P/N 12V for each load (DAC, and each opamp)? There will be some AC leakage via D5A/B capacitance etc. Also R3 can be at least <100R safely.

I think additional LC filter makes sense to add for the DAC DVCC line at least to reduce the return AC current via C83, C13, C14 to the power supply that can leak to the analog side.

I think it makes sense add additional inductor similar to L8 and power IC1 and IC35 separately so it will reduce cross-interference.

It makes sense to route the IC3 and related parts ground directly to IC18 AGND pins (star routing) but not to the gnd plane. Also it makes sense to have the ground plane between the front panel side cut under most of the boards and have connected only under the DAC so it will prevent parasitic digital ground noise.

I can check the layout as well. According the DAC d/s it is quite sensitive for the layout and grounding.

[hartytp]

@a-shafir

How about separate with beads the P/N 12V for each load (DAC, and each opamp)?

I don't believe that a ferrite bead on each OpAmp would be helpful; SMT ferrites typically only work for 10s of MHz and above, but this circuit only works at audio frequencies so their effect will be minimal. I also do not believe that a ferrite between the DAC's analog supply rails and the OpAmps is helpful for the same reason.

Note that there is already heavy LC filtering between the SMPS and the LDOs.

All digital circuitry (which has frequencies that could benefit from a ferrite bead) is already run from a different regulator to the analog circuitry (it's 3V3).

There will be some AC leakage via D5A/B capacitance etc.

Really? The capacitance for those diodes is of order 1pF. That forms a pole at 300MHz with the 500Ohm output impedance. Again, given that this circuit is only designed to operate at audio frequencies, and that the supply rails are very low noise, that will not be a problem. Moreover, the DAC output capacitor is 2.2nF, a thousand times larger and so will filter off any small noise coupled from the supply rails.

Also R3 can be at least <100R safely.

It potentially could be, but there should be no need for that; those regulators should be very low noise already. Let's wait until we start making noise measurements and only change this if we find a problem.

I think additional LC filter makes sense to add for the DAC DVCC line at least to reduce the return AC current via C83, C13, C14 to the power supply that can leak to the analog side.

I don't understand what you mean here. You want to put an inductor between the DAC and the decoupling capacitors to prevent digital currents returning to ground through those caps? That's not a good idea. This supply is absolutely fine IMHO and not going to cause any problems.

Let's leave this as it is for now. We will test the prototypes carefully for noise issues and make changes are required.

I think it makes sense add additional inductor similar to L8 and power IC1 and IC35 separately so it will reduce cross-interference.

Really not necessary. If a small amount of noise couples from the input of one switch mode supply to the input of another that won't be a problem -- a tiny amount of cross-talk between the supplies won't degrade their overall performance and they are already heavily filtered on their outputs.

It makes sense to route the IC3 and related parts ground directly to IC18 AGND pins (star routing) but not to the gnd plane.

No, I'd prefer not to do this. These kinds of ground plane cuts are rarely a good idea. Better to do this with a good layout that keeps the reference near the DAC and ensures that both share a low impedance ground-plane.

Also it makes sense to have the ground plane between the front panel side cut under most of the boards and have connected only under the DAC so it will prevent parasitic digital ground noise.

No! Again, these kinds of ground cuts are generally not a good idea and usually cause more problems than they solve.

[hartytp]

@a-shafir I appreciate the enthusiasm for improving these boards. But, for now I don't want to make those kinds of changes. Your approach would overcomplicate these designs by adding components to try to solve things that are unlikely to be issues.

Let's just wait until we have the next prototype. Once we've characterised that thoroughly we can see what the actual performance is and evaluate changes based on that. If the performance is bad then we can consider making a new version with some of these modifications.

[a-shafir]

Ok, about the ground plane this is exactly type of the circuit where it works perfectly. The digital part of the board is quite noisy and imho there is no reasons to spread the return currents via whole board ground/power planes. Even this looks like over-caution it certainly will not harm in this board where there is only one A-D junction but might help. It cost nothing including the design. There is no reason to afraid the "analog ground" - it only helps in most of the cases. I am not suggesting a full ground separation with beads etc - this indeed can be dangerous in many cases.

Note: i have not seen any single audio DAC with no significant noise in a solid ground plane.

Basically i see only not well under control noise source - the ground. Including the VREF signal path.

Some simple numbers: reactive impedance of a trace 100mm wide 0.5oz copper is ~0.000247Ohm so 1A DC current will be 0.24mV drop. The DAC resolution on the output roughly 10V/2^16 ~= 0.15mV. So it is in the same scale. With AC it worst, roughly 10 times at 77KHz.

BTW: in case of using peltier cooler it makes sense to have proper cleaning and possible conformal coating in the affected area because the it leads to condensation etc.

[hartytp]

Some simple numbers: reactive impedance of a trace 100mm wide 0.5oz copper is ~0.000247Ohm so 1A DC current will be 0.24mV drop. The DAC resolution on the output roughly 10V/2^16 ~= 0.15mV. So it is in the same scale. With AC it worst, roughly 10 times at 77KHz.

Firstly, this statement makes no sense. Reactive impedance of a trace at DC? You mean resistive? Where do you get 1A from? What kind of digital logic has that kind of current? I appreciate the effort to quantify your statements, but this calculation is irrelevant.

Even this looks like over-caution it certainly will not harm in this board where there is only one A-D junction but might help.

I disagree with this statement. It's really easy to take a perfectly good board and ruin it by splitting ground planes.

Also, note that there is a pretty aggressive output filter on these boards that will make a large difference to any high-frequency digital noise.

---

As the one funding this project, here is an executive decision on this matter to avoid wasting time on it: unless @gkasprow says it's necessary, we will not do this for the prototypes. If there is a noise issue (beyond the expected clock feedthrough, LDAC glitches etc) with them then we will reconsider in a future revision

---

BTW: in case of using peltier cooler it makes sense to have proper cleaning and possible conformal coating in the affected area because the it leads to condensation etc.

If you're getting condensation on the peltier here then you're doing something wrong.

[hartytp]

@a-shafir re diode capacitance. Note that the regulators we're using on this board negative LOD data sheet positive LDO datasheet have noise floors below 100nV/rtHz. So, for higher frequencies, that's divided by 1000:1 by the output capacitor, giving a noise floor for the board below 100pV/rtHz.

At lower frequencies the supply noise is larger, but it's shunted more effectively by the 500R output resistor.

So, unless there are some large spurs on the regulator (e.g. leakage due to the SMPS) I do not expect an issue. If we see those then we will definitely add an LC filter/ferrite bead/etc.

[hartytp]

@gkasprow On this subject: @a-shafir's posts did make me look again at the supply network (so, thanks for that) so I noticed that the negative LDO we're using is the version without the bypass pin. As this is quite a noise sensitive device, we should probably use the bypassable version unless there is a good reason no to (e.g. big cost difference). Why didn't we use it?

NB If we change this on Zotino, we should also change it on all other boards using this regulator (is that just sampler?).

[hartytp]

@gkasprow I had more of a look at the measurement setup we were using here to look at the noise. Based on my new measurements, I currently believe that the noise @cjbe saw is related to the measurement setup and not to the DAC itself.

So, I don't think there is any need to do further testing on the v1.1 boards.

[jordens]

@Hartytp Care to elaborate?

[hartytp]

I think the bulk of what Chris was seeing was pickup/grounding/wiring issues.

I'm now using a small coax pigtail soldered directly to the output of the CMC on Zotino to do my probing (DAC removed, OpAmp input grounded). I'm attaching that to a low noise FFT analyzer. I measure a noise floor of something like 17nV/rtHz with lots of junk on it at higher frequencies (instrument noise floor is around 5nV/rtHz). However, AFAICT, all that high frequency junk is just pickup (I see a similar spectrum, but with at a much larger level with the board unpowered). e.g. the noise floor depends more on whether the PSU is plugged in (output off) than whether the board is actually powered.

But, these are the standard low-noise measurement issues one always sees. Doing this measurement properly isn't that hard, just a bit time consuming (battery powered pre-amps, careful wiring and grounding etc) and I don't have time to do it right now.

My feeling is that we should do this all properly once we have the v1.2 design and not spend any more time on the current boards.

[hartytp]

@jordens Maybe I'll regret saying this, but I'm not too worried about the filter design, which is the only thing I can test at the moment (e.g. can't test the DACs because they die too fast) so I think it makes sense to move onto v1.2 without further delay.

The filter itself is just an OpAmp circuit. We've simulated it in SPICE and it looks good. But even if there is a problem there, I'm confident that we can make it work by changing component values/OpAmps. So, the only real danger is noise sources external to the filter, such as:

• The DACs/digital stuff: this could be a serious issue, but I can't test it at the moment.
• The SMPSs: from Sampler, we know that these SMPSs can be used in very low noise designs without issue; that design achieved 8nV/rtHz (consistent with the InAmp noise floor) and if we had to, we could live with that for this design since we will generally have a filter by the trap which can provide the final 20dB.
• External pickup: not much we can do about that apart from add external screening (the layout is already pretty good and we do already have CMCs etc).

[gkasprow]

@hartytp the TEC wires holes are 1.1mm. Should be fine. IDC contact current is usually rated 1A. I added 2 more pins and bigger IDC connector. Do we really need 15x15mm TEC? I was thinking about 9x9 one... The I2C extender is also routed to the DAC reset pin. I'm not sure if anyone is going to use that. OK, let's remove cutouts and make more space for TEC and mounting I changed the LDO to LT1964ES5-BYP#TRMPBF There are already cut-outs around theSMPS to limit the return current

[gkasprow]

It's not easy to find small heatsink with mounting holes...

[hartytp]

The I2C extender is also routed to the DAC reset pin. I'm not sure if anyone is going to use that.

I'd be happy to just get rid of it -- I don't think that I2C is needed for the temperature controller or the DAC RESET. @jordens any objections?

IDC contact current is usually rated 1A. I added 2 more pins and bigger IDC connector. Do we really need 15x15mm TEC? I was thinking about 9x9 one...

9x9 should be fine. Just make sure it's a standard size and that there are few Watt TECs available that are close to 2.5Ohm (so that they are well matched to that Maxim peltier driver chip that we will probably use).

OK, let's remove cutouts and make more space for TEC and mounting

Sounds good. Let's just make sure that the thermal simulations show that a few Watt TEC will be able to change the DAC temperature by a degree or two.

[hartytp]

It's not easy to find small heatsink with mounting holes...

What do you want to do then? Glue it? Or, are there PCB mount clips we can use to hold it in place? I don't mind what you do here so long as there is some easy way of mounting it.

[gkasprow]

TEC modules need quite a lot of force to work properly. Let's use this type of thing. I use bigger version of them. The yellow frame will hold Peltier module, I will add PCB-mounted hooks for the springs

[hartytp]

@gkasprow That looks good. I'd be happy to go for something like that.

Please can you add a suitable TEC and heatsink to the BOM? It would be good to populate this for the test boards so that we can check it all works during prototyping. (For that I would probably use the evaulation board that Thorlabs sell, which hooks up to USB and does PID + peltier driver).

[gkasprow]

I mean such jumpers that are sold as components and will manage to keep such assembly

[hartytp]

@gkasprow That sounds good. I just mean that it would be good to also choose a TEC + heatsink + clip and attach it to the PCB. That checks it all fits together and also allows us to make measurements like temperature stability of the DAC more easily.

[gkasprow]

sure, let's add it to the BOM. I will also make mechanical models to make sure it fits.

[hartytp]

great!

[gkasprow]

@jordens @hartytp we can leave I2C, then add I2C <-> UART bridge chip and control TEC controller from Zotino board directly

[gkasprow]

@hartytp Such TEC should do the job..

[gkasprow]

Edit - I mean 10x10 modules, 15x15 are slightly too big. such one

[gkasprow]

but 15x15 are much cheaper...

[gkasprow]

OK, I will fit 15x15 as well. What about 2.6V module?

[gkasprow]

This one should be fine

[hartytp]

but 15x15 are much cheaper...

Yes, AFIACT, 15x15 is standard so it's best to go for that if we can.

What about 2.6V module?

Let's go for one with closer to 2.6Ohm so it works with the nice Maxim TEC driver (1.5A, 4V)

@jordens @hartytp we can leave I2C, then add I2C <-> UART bridge chip and control TEC controller from Zotino board directly

Okay, I'm fine to leave the I2C there if it doesn't make much difference to the size of the connector. Even if Thermostat supports ethernet as its main interface, having an I2C interface as well would be nice. That way, it becomes just an extension of Zotino.

I guess we can mount the TEC driver board on a separate front panel adjacent to Zotino.

[jordens]

I think we can live without reset. If the power on sequence leads to a well defined state. The datasheet does not say much about the sequencing of the reset. Since we are now looking at a TEC with heating and cooling, we can lower the thermal resistance between the DAC and the board as much as possible. The reason is to guarantee that this board will work well even without the TEC and associated logic. The only limit there is that the TEC needs to be able to heat away the all of the DAC power fluctuations times the ratio of the thermal resistances (ambient-TEC-DAC/DAC-board-ambient). That ratio should probably be above 0.5 given that the TEC can do +-2W and a cautious estimate for DAC power fluctuation of +-1W.

[hartytp]

I think we can live without reset. If the power on sequence leads to a well defined state. The datasheet does not say much about the sequencing of the reset.

FWIW, I don't recall ever using the reset pin for these DACs. IIRC, I've only ever used the SPI interface to do everything and that's always been fine.

@jordens Do you need the BUSY pin (or CLR for that matter) on the EEM connector? One other option would be to take BUSY/CLR of the EEM connector and to put RESET directly on the EEM connector (more convenient than having it on I2C anyway).

---

In any case, as @gkasprow points out, it's probably worth keeping the I2C interface there for the temperature controller. If something like Thermostat is used to control Zotino, it's nice if it can be wired as basically being an I2C extension of Zotino (gains and setpoint programmed automatically on startup by Kasli) rather than needing an extra ethernet cable.

[hartytp]

Since we are now looking at a TEC with heating and cooling, we can lower the thermal resistance between the DAC and the board as much as possible. The reason is to guarantee that this board will work well even without the TEC and associated logic. The only limit there is that the TEC needs to be able to heat away the all of the DAC power fluctuations times the ratio of the thermal resistances (ambient-TEC-DAC/DAC-board-ambient). That ratio should probably be above 0.5 given that the TEC can do +-2W and a cautious estimate for DAC power fluctuation of +-1W.

Agreed, that's the current plan. As @gkasprow said in a post above, he's removed the thermal island completely.

He's also planning to do a thermal simulation to check the C/W of the peltier and check that's it's something sensible (aiming for something like 1C/W).

[hartytp]

@gkasprow To confirm: in the initial prototypes we're planning to get Technosystems to populate the peltier stack (including heat sinks etc), right?

[gkasprow]

Yes. I'm not sure if I manage to do the thermal simulation with TEC. I never did it before :) I used simplified Hyperlynx tool for PCB level simulations. For TEC simulation, I have to dig into the FloTherm package. I'll do it once we close issues that cannot wait.

[hartytp]

I'm not sure if I manage to do the thermal simulation with TEC. I never did it before :)

Can you do this by adding a 1W resistor connected to ground where the TEC should go? See how much the DAC temperature changes with and without the resistor and that tells you everything you need to know.

[gkasprow]

This I can do. Maybe it's possible to specify negative power :) I will check

[hartytp]

You don't need to simulate negative power; the number of C/W will be about the same for positive and negative power. So, just simulate with a resistor delivering positive power and it will be fine! We just need a rough estimate of this to check that we're in the right ball park, we're not looking for something ultra-precise.

[jordens]

If your tools can't simulate that directly, we need to know two new thermal resistances. "junction-package-TEC" (from the DAC datasheet and a good number for the thermal contact of the TEC) and "TEC-ambient" (including the TEC heat sink). The third resistance "junction-board-ambient" is known and is what Greg has been simulating. Then with the efficiency P_thermal/P_electrical(delta T) of the TEC, whever wants to have a go at this can set up the thermal circuit.

[gkasprow]

I can add 1W of heat source, no problem.

[hartytp]

I can add 1W of heat source, no problem.

Great! That gives enough information to check that this will work.

Remember that we only need to take our DAC's temperature fluctuations from a few degress to a few hundred mK, so this isn't a very demanding application. As a result, I'm happy ignoring things like the DAC-ambient thermal impedance (if this is an issue then we can glue insulating foam over the DAC).

[jordens]

@gkasprow Just out of curiosity: The four mounting holes in each EEM PCB that have so far been unused, do they by chance fit the slots for nuts and screws in these heat sinks?

With a spacer between PCB underside and heat sink to make some clearance for SMD parts that could be a simple solution to cooling certain parts of these EEMs, like Urukul or Zotino.